ovpanait / zynq-aes
AES hardware engine for Xilinx Zynq platform
☆29Updated 3 years ago
Alternatives and similar repositories for zynq-aes:
Users that are interested in zynq-aes are comparing it to the libraries listed below
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆39Updated last year
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆36Updated 5 years ago
- IEEE P1735 decryptor for VHDL☆29Updated 9 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- Verilog Ethernet Switch (layer 2)☆39Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- AHB3-Lite Interconnect☆83Updated 8 months ago
- A demo system for Ibex including debug support and some peripherals☆60Updated 4 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- ☆53Updated 2 years ago
- Verilog RTL Design☆30Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- ☆20Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated last month
- Implementation of the PCIe physical layer☆32Updated this week
- AXI4 and AXI4-Lite interface definitions☆88Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Interface Protocol in Verilog☆49Updated 5 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆33Updated last year
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- PCIE 5.0 Graduation project (Verification Team)☆57Updated 11 months ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆66Updated 7 months ago