ovpanait / zynq-aesLinks
AES hardware engine for Xilinx Zynq platform
☆31Updated 3 years ago
Alternatives and similar repositories for zynq-aes
Users that are interested in zynq-aes are comparing it to the libraries listed below
Sorting:
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆38Updated 5 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated last month
- Implementation of the PCIe physical layer☆42Updated last month
- ☆67Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆72Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Verilog based BCH encoder/decoder☆120Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- IEEE P1735 decryptor for VHDL☆32Updated 10 years ago
- Verilog Ethernet Switch (layer 2)☆44Updated last year
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆15Updated 2 years ago
- Hardware Viterbi Decoder in verilog☆26Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- ☆21Updated 5 years ago
- Hardware Assisted IEEE 1588 IP Core☆29Updated 10 years ago