Alternatives and similar repositories for edif-parser:

Users that are interested in edif-parser are comparing it to the libraries listed below

• bunnie / netlist-checker
  EDIF netlist checker tool
  ☆25Updated 2 years ago
• x-epic / EpicFV
  ☆20Updated 3 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 4 years ago
• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 7 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆12Updated 5 years ago
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• amromanov / vmodel
  Vmodel toolbox repository
  ☆14Updated 8 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆35Updated 11 months ago
• varunnagpaal / Analog-Design-Modelling
  Analog Hardware Hands on Design Labs and Modelling using SPICE Tools (NI Multisim, LTSpice)
  ☆24Updated 6 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆55Updated last month
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 8 years ago
• firesim / aws-fpga-firesim
  AWS Shell for FireSim
  ☆12Updated 3 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 7 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 6 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• verilog-to-routing / libsdcparse
  ☆11Updated 5 years ago
• jeras / sockit_owm
  SocKit 1-wire (onewire) master
  ☆19Updated 12 years ago
• sergachev / litex-template
  Template project for LiteX-based SoCs
  ☆19Updated 7 months ago
• russdill / darter
  SPICE based IBIS simulation
  ☆13Updated last month
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago