litaotju / edif-parserLinks
A c project for EDIF format parse.
☆13Updated 9 years ago
Alternatives and similar repositories for edif-parser
Users that are interested in edif-parser are comparing it to the libraries listed below
Sorting:
- EDIF netlist checker tool☆26Updated 2 years ago
- EpicSim Project☆71Updated 4 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 10 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆80Updated 3 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆16Updated last week
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Framework Open EDA Gui☆68Updated 7 months ago
- SocKit 1-wire (onewire) master☆19Updated 12 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- Magma Hackathon☆12Updated 5 years ago
- This store contains Configurable Example Designs.☆48Updated this week
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 weeks ago
- Template project for LiteX-based SoCs☆21Updated last month
- Chisel Things for OFDM☆32Updated 5 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆39Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Intel Compiler for SystemC☆23Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- The source code that empowers OpenROAD Cloud☆12Updated 5 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆95Updated 5 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Cortex-M0 DesignStart Wrapper☆19Updated 5 years ago
- ☆56Updated 3 years ago
- TeleBench™ is a suite of benchmarks that allows the users to approximate the performance of processors in modem and related fixed-telecom…☆12Updated 4 years ago
- ☆31Updated this week