Alternatives and similar repositories for edif-parser

Users that are interested in edif-parser are comparing it to the libraries listed below

• x-epic / EpicSim
  EpicSim Project
  ☆71Updated 4 years ago
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆99Updated 7 months ago
• bunnie / netlist-checker
  EDIF netlist checker tool
  ☆26Updated 2 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆65Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆87Updated 11 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆38Updated 2 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆114Updated this week
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆50Updated 6 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆49Updated last month
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆47Updated 2 years ago
• daitoto / EDA-wiki
  EDA wiki
  ☆53Updated 2 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆155Updated 3 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆22Updated 9 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆24Updated 2 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated this week
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆123Updated 10 months ago
• wavedrom / vcd
  Value Change Dump (VCD) parser
  ☆38Updated 8 months ago
• scutdig / PyChip-py-hcl
  A Hardware Construct Language
  ☆43Updated 3 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆62Updated 3 weeks ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆100Updated 3 years ago
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆21Updated last year
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆230Updated this week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆45Updated last year