Alternatives and similar repositories for edif-parser

Users that are interested in edif-parser are comparing it to the libraries listed below

• x-epic / EpicSim
  EpicSim Project
  ☆71Updated 4 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago
• bunnie / netlist-checker
  EDIF netlist checker tool
  ☆26Updated 2 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆31Updated 5 years ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆41Updated 9 months ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆97Updated 3 years ago
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆97Updated 6 months ago
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆49Updated 4 months ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆65Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆83Updated 10 months ago
• scutdig / PyChip-py-hcl
  A Hardware Construct Language
  ☆43Updated 3 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆63Updated last year
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆111Updated last week
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 8 months ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆21Updated last year
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆24Updated 2 years ago
• ahmed-agiza / EDAViewer
  EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
  ☆72Updated 2 years ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• daitoto / EDA-wiki
  EDA wiki
  ☆53Updated 2 years ago
• grebe / ofdm
  Chisel Things for OFDM
  ☆32Updated 5 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• pkuzjx / EDA-wiki
  EDA wiki
  ☆131Updated 4 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆162Updated 2 months ago