openMSP430 CPU core (from OpenCores)
☆22Oct 14, 2022Updated 3 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 11 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Cycle accurate MC6502 compatible processor in Verilog.☆16Oct 11, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- UART 16550 core☆39Jul 17, 2014Updated 11 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- ☆11Jul 16, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Mini RISC-V CPU☆10Dec 26, 2019Updated 6 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 6 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 6 years ago
- Windows PE file debugger☆11Aug 30, 2017Updated 8 years ago
- ☆19Jul 21, 2020Updated 5 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆15Dec 1, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.☆14Jan 27, 2016Updated 10 years ago
- ☆11Jul 4, 2023Updated 2 years ago
- ☆11Jul 16, 2020Updated 5 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- An CAN bus Controller implemented in Verilog☆53May 28, 2015Updated 10 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 12 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- MS-DOS 4.0 fork, with tweaks to make it run on the Envy OS as a subsystem.☆17May 22, 2024Updated last year
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year
- 基于玄铁openc906，搭建最小化SoC系统☆20Apr 7, 2025Updated last year
- 8051 core☆112Jul 17, 2014Updated 11 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago