dlitz / openmsp430Links
openMSP430 CPU core (from OpenCores)
☆22Updated 2 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below
Sorting:
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆88Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- JTAG Test Access Port (TAP)☆34Updated 11 years ago
- Generic AXI master stub☆19Updated 11 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- ☆30Updated 8 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- PCI bridge☆18Updated 11 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- UART 16550 core☆37Updated 11 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Wishbone SATA Controller☆19Updated last month
- ☆19Updated 11 years ago
- Ethernet 10GE MAC☆45Updated 11 years ago