openMSP430 CPU core (from OpenCores)
☆22Oct 14, 2022Updated 3 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 11 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Cycle accurate MC6502 compatible processor in Verilog.☆16Oct 11, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Pipelined DCPU-16 Verilog Implementation☆42May 30, 2012Updated 13 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- UART 16550 core☆40Jul 17, 2014Updated 11 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- A pipeline CPU in Verilog for the Y86 instruction set.☆28Dec 18, 2014Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Intel Management Engine JTAG Proof of Concept☆21Nov 14, 2019Updated 6 years ago
- Mini RISC-V CPU☆11Dec 26, 2019Updated 6 years ago
- A CPU Backdoor. Phrack 72☆15Dec 4, 2025Updated 5 months ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- ☆13Sep 23, 2024Updated last year
- Wishbone SATA Controller☆26Oct 16, 2025Updated 7 months ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆19Jul 21, 2020Updated 5 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆16Dec 1, 2023Updated 2 years ago
- Verilog VGA font generator 8 by 16 pixels☆16Mar 30, 2022Updated 4 years ago
- ☆14Oct 19, 2018Updated 7 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.☆14Jan 27, 2016Updated 10 years ago
- ☆11Jul 4, 2023Updated 2 years ago
- Recursive unified ORAM☆16Sep 23, 2015Updated 10 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- An CAN bus Controller implemented in Verilog☆53May 28, 2015Updated 10 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 12 years ago
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated last year
- MS-DOS 4.0 fork, with tweaks to make it run on the Envy OS as a subsystem.☆17May 22, 2024Updated 2 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year
- 基于玄铁openc906,搭建最小化SoC系统☆21Apr 7, 2025Updated last year