Alternatives and similar repositories for MIPS-Verilog

Users that are interested in MIPS-Verilog are comparing it to the libraries listed below

• luuvish / system-verilog-patterns
  SystemVerilog Design Patterns
  ☆26Updated 10 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated 11 months ago
• grantae / mips32r1_core
  A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
  ☆19Updated 10 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆109Updated 6 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• sveditor / sveditor
  SystemVerilog Development Environment
  ☆54Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆125Updated 10 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆34Updated 11 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 7 months ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆88Updated 8 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆46Updated 10 years ago
• cjdrake / AES
  Advanced Encryption Standard (AES) SystemVerilog Core
  ☆34Updated 7 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆112Updated 2 weeks ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• bsg-idea / uw_openroad_free45
  UW reference flow for Free45PDK and The OpenROAD Project
  ☆11Updated 5 years ago
• freecores / robust_axi2apb
  Generic AXI to APB bridge
  ☆13Updated 11 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 5 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago