Alternatives and similar repositories for MiteCPU

Users that are interested in MiteCPU are comparing it to the libraries listed below

• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 7 months ago
• AngelTerrones / Algol
  A RISC-V CPU (Outdated: using priviledge v1.7)
  ☆26Updated 6 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 5 months ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆54Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆47Updated 8 months ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆44Updated 3 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆48Updated 2 months ago
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆24Updated 3 weeks ago
• gundy / tinyfpga-bx-game-soc
  A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
  ☆23Updated 6 years ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆17Updated 3 years ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆36Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆33Updated 2 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• wel97459 / FPGACosmacELF
  A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
  ☆42Updated 4 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 6 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆42Updated 7 years ago
• Anding / N.I.G.E.-Machine
  A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…
  ☆28Updated last month
• mattvenn / fpga-sram
  mystorm sram test
  ☆29Updated 8 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆25Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆42Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆19Updated 4 years ago
• lzw545 / opengg
  OpenGL-like graphics pipeline on a Xilinx FPGA
  ☆33Updated 14 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago