jbush001 / MiteCPU
Minimal microprocessor
☆20Updated 7 years ago
Alternatives and similar repositories for MiteCPU:
Users that are interested in MiteCPU are comparing it to the libraries listed below
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated this week
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆25Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 weeks ago
- A reimplementation of a tiny stack CPU☆82Updated last year
- Reusable Verilog 2005 components for FPGA designs☆41Updated last month
- CMod-S6 SoC☆40Updated 7 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆54Updated last week
- A design for TinyTapeout☆16Updated 2 years ago
- A bit-serial CPU☆18Updated 5 years ago
- Efficient implementations of the transcendental functions☆27Updated 8 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆22Updated 6 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- RISC-V processor☆29Updated 2 years ago
- Tools for FPGA development.☆44Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆28Updated 4 months ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- A very simple UART implementation in MyHDL☆17Updated 10 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆16Updated 6 years ago
- Yosys Plugins☆21Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago