drom / quark
Stack CPU Work In Progress
☆30Updated last year
Alternatives and similar repositories for quark:
Users that are interested in quark are comparing it to the libraries listed below
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆27Updated 2 months ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- Yet Another Forth Core...☆71Updated 10 years ago
- eForth for the j1 simulator and actual J1 FPGAs☆34Updated 9 years ago
- http://mecrisp.sourceforge.net/ Mecrisp-Ice is an enhanced version of Swapforth and the J1a stack processor by James Bowman, featuring th…☆28Updated 8 years ago
- Compiler, loader, and simulator for the GA144 multi-computer chip☆31Updated 5 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆59Updated 5 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- Synthesis-Aided Compiler for GreenArrays GA144☆52Updated 8 years ago
- Yosys Plugins☆21Updated 5 years ago
- Hardware/Software Co-design environment of a processor core for deterministic real time systems☆37Updated last year
- Efficient implementations of the transcendental functions☆26Updated 8 years ago
- Forth for the J1-CPU☆18Updated 7 years ago
- A bit-serial CPU☆18Updated 5 years ago
- ☆58Updated last year
- CCPU for GA144☆22Updated 6 years ago
- OpenFPGA☆33Updated 6 years ago
- Stack machine with 4-bit instructions☆73Updated 7 years ago
- Finds optimal code sequences for stack transformations☆24Updated 5 years ago
- a simple C-to-Verilog compiler☆48Updated 7 years ago
- A reimplementation of a tiny stack CPU☆81Updated last year
- Python based tool chain for the GA144 multi-computer chip☆18Updated last year
- Forth bindings for the FTDI FT800/Gameduino2☆22Updated 9 years ago
- A microcontroller that natively executes a simple LISP dialect☆90Updated last year
- A 6800 CPU written in nMigen☆48Updated 3 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Forth for RISC-V SBCs☆31Updated 2 months ago
- A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.☆49Updated 3 years ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆25Updated 5 years ago
- A Racket-based Forth / Macro Assembler on steroids for PIC18F☆40Updated last year