PythonLinks / awesome-risc-v-soft-coresLinks
Compares the different RISC-V soft cores in order to help you select the best one for your application.
☆13Updated 3 months ago
Alternatives and similar repositories for awesome-risc-v-soft-cores
Users that are interested in awesome-risc-v-soft-cores are comparing it to the libraries listed below
Sorting:
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆32Updated last year
- ☆18Updated 5 months ago
- Utilities for working with a Wishbone bus in an embedded device☆46Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- System on Chip toolkit for Amaranth HDL☆93Updated 11 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆56Updated 5 months ago
- FLIX-V: FPGA, Linux and RISC-V☆42Updated last year
- Design digital circuits in C. Simulate really fast with a regular compiler.☆173Updated 2 years ago
- Virtual Development Board☆62Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Exploring gate level simulation☆58Updated 5 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆110Updated last year
- A pipelined RISC-V processor☆61Updated last year
- Board definitions for Amaranth HDL☆119Updated last month
- A Risc-V SoC for Tiny Tapeout☆37Updated this week
- ☆55Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 7 months ago
- Soft USB for LiteX☆50Updated this week
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 4 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆102Updated 2 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆90Updated 3 months ago
- Documenting the Lattice ECP5 bit-stream format.☆55Updated 2 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- Simulation VCD waveform viewer, using old Motif UI☆27Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 8 months ago
- Optimized RISC-V FP emulation for 32-bit processors☆36Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- ☆43Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆54Updated 2 weeks ago