PythonLinks / awesome-risc-v-soft-coresLinks
Compares the different RISC-V soft cores in order to help you select the best one for your application.
☆13Updated 5 months ago
Alternatives and similar repositories for awesome-risc-v-soft-cores
Users that are interested in awesome-risc-v-soft-cores are comparing it to the libraries listed below
Sorting:
- ☆18Updated 6 months ago
- FLIX-V: FPGA, Linux and RISC-V☆41Updated 2 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆32Updated last year
- Virtual Development Board☆64Updated 3 years ago
- IRSIM switch-level simulator for digital circuits☆35Updated last week
- Exploring gate level simulation☆58Updated 7 months ago
- ☆27Updated 6 years ago
- Utilities for working with a Wishbone bus in an embedded device☆46Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated last week
- Soft USB for LiteX☆50Updated last month
- ☆55Updated 3 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 2 weeks ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated 9 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆57Updated last week
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆34Updated 2 years ago
- GDB server to debug CPU simulation waveform traces☆43Updated 3 years ago
- Documenting the Lattice ECP5 bit-stream format.☆56Updated 2 years ago
- yosys, nextpnr, apicula and openFPGALoader in vscode using OSS-CAD-Suite☆37Updated last year
- Experiments with Yosys cxxrtl backend☆50Updated 10 months ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆26Updated 6 years ago
- Board definitions for Amaranth HDL☆121Updated 2 months ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- A 6800 CPU written in nMigen☆49Updated 4 years ago
- A Risc-V SoC for Tiny Tapeout☆43Updated last week
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 5 years ago
- A pipelined RISC-V processor☆62Updated last year
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- FPGA 101 - Workshop materials☆77Updated 6 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago