PythonLinks / awesome-risc-v-soft-coresLinks
Compares the different RISC-V soft cores in order to help you select the best one for your application.
☆14Updated 7 months ago
Alternatives and similar repositories for awesome-risc-v-soft-cores
Users that are interested in awesome-risc-v-soft-cores are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last week
- Virtual Development Board☆64Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- IRSIM switch-level simulator for digital circuits☆36Updated 2 months ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Updated last year
- Small footprint and configurable Inter-Chip communication cores☆66Updated last week
- A Risc-V SoC for Tiny Tapeout☆48Updated 2 months ago
- FLIX-V: FPGA, Linux and RISC-V☆42Updated 2 years ago
- Utilities for working with a Wishbone bus in an embedded device☆47Updated 5 months ago
- A bit-serial CPU☆19Updated 6 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Updated 2 months ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆26Updated 6 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- ☆20Updated 9 months ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Experiments with Yosys cxxrtl backend☆50Updated last year
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆68Updated 9 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- Another size-optimized RISC-V CPU for your consideration.☆59Updated last week
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year
- ☆15Updated 8 months ago
- A design for TinyTapeout☆18Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33Updated 5 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- verilator testbench w/ Javascript using N-API☆18Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆24Updated 4 years ago
- PicoRV☆43Updated 5 years ago