BerkeleyLab / BedrockLinks
LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
☆60Updated this week
Alternatives and similar repositories for Bedrock
Users that are interested in Bedrock are comparing it to the libraries listed below
Sorting:
- An open-source HDL register code generator fast enough to run in real time.☆68Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆43Updated 4 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆68Updated 8 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆6Updated last week
- Extensible FPGA control platform☆62Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆63Updated last week
- UART models for cocotb☆29Updated 2 years ago
- ☆21Updated last month
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- ☆32Updated 2 years ago
- Control and Status Register map generator for HDL projects☆116Updated last week
- assorted library of utility cores for amaranth HDL☆92Updated 8 months ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆162Updated 3 years ago
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- Drawio => VHDL and Verilog☆55Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- I2C models for cocotb☆35Updated 2 months ago
- Framework Open EDA Gui☆65Updated 5 months ago
- FPGA and Digital ASIC Build System☆74Updated 2 weeks ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 4 months ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆27Updated 11 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆28Updated 4 months ago