BerkeleyLab / Bedrock
LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
☆54Updated this week
Alternatives and similar repositories for Bedrock:
Users that are interested in Bedrock are comparing it to the libraries listed below
- Extensible FPGA control platform☆55Updated last year
- assorted library of utility cores for amaranth HDL☆85Updated 4 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆40Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 4 months ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Small footprint and configurable JESD204B core☆40Updated last week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated this week
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆32Updated 4 months ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆32Updated this week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- IEEE P1735 decryptor for VHDL☆29Updated 9 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆22Updated 6 months ago
- A collection of phase locked loop (PLL) related projects☆100Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆26Updated this week
- ☆39Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆90Updated 4 years ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆28Updated last month
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆70Updated 3 years ago
- A simple DDR3 memory controller☆53Updated 2 years ago
- ☆30Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆52Updated this week
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- ☆32Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Framework Open EDA Gui☆63Updated last month
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆35Updated 3 years ago