Alternatives and similar repositories for Bedrock

Users that are interested in Bedrock are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated 3 weeks ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆79Updated 3 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆64Updated 2 months ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆94Updated last year
• ldoolitt / vhd2vl
  ☆139Updated 3 weeks ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆116Updated 2 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆121Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆129Updated 8 months ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆97Updated 5 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆169Updated 3 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆88Updated 3 months ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 4 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated 2 months ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆51Updated 3 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆61Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆129Updated 8 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago