Digital HDL Design Full-stack Agents
☆208Oct 2, 2026Updated this week
Alternatives and similar repositories for digital-chip-design-agents
Users that are interested in digital-chip-design-agents are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆51Aug 3, 2026Updated 2 months ago
- pyslang-mcp is a read-only Model Context Protocol server for compiler-backed Verilog and SystemVerilog analysis. It uses pyslang to parse…☆21Jun 14, 2026Updated 3 months ago
- Dr.RTL: Autonomous Agentic RTL optimization through Tool-Grounded Self-Improvement☆31Sep 4, 2026Updated 3 weeks ago
- opensource NPU for LLM inference (this run gpt2)☆258Feb 16, 2026Updated 7 months ago
- RTL agent team; Harness for Agentic hardware design and verificiation.☆53Aug 23, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- libView is a GUI tool for library file cell information view and comparison.☆27Jul 24, 2023Updated 3 years ago
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆112Jul 29, 2025Updated last year
- ☆16May 6, 2026Updated 4 months ago
- Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM s…☆118Sep 25, 2026Updated last week
- DeepGate3 for ICCAD2024☆14May 26, 2025Updated last year
- ☆17Jul 26, 2026Updated 2 months ago
- Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP sp…☆24Jul 14, 2026Updated 2 months ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆209Jan 28, 2026Updated 8 months ago
- ☆15Oct 8, 2024Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ARCH hardware description language and compiler☆78Updated this week
- Collection for agent skills on analog and mixed-signal (AMS) IC (integrated circuit) design☆32Jun 5, 2026Updated 3 months ago
- ☆36Jun 18, 2026Updated 3 months ago
- AI-Powered Hardware Design & Verification Copilot - Plugin for your CLI☆22Jul 12, 2026Updated 2 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 8 months ago
- SystemVerilog file list pruner☆19Sep 14, 2026Updated 2 weeks ago
- dskill — SKILL Decompiler on RHEL7/CentOS7 (glibc 2.17). Binary-only release.☆18May 12, 2026Updated 4 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆140Apr 11, 2025Updated last year
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆27Updated this week
- A curated, community-maintained list of ML/LLM research and tools for integrated-circuit design — across the full flow.☆26Aug 4, 2026Updated last month
- [ICCD2026] CPPL: A Circuit Prompt Programming Language☆21Aug 19, 2026Updated last month
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆325Feb 9, 2025Updated last year
- RTL data structure☆69Apr 23, 2026Updated 5 months ago
- Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations☆14Jan 22, 2020Updated 6 years ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆1,105Updated this week
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆35Feb 24, 2026Updated 7 months ago
- UnityChip Verification AI-Agent☆229Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆303Sep 30, 2025Updated last year
- ☆15May 24, 2025Updated last year
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 11 months ago
- This is the repository for the IEEE version of the book☆87Sep 29, 2020Updated 6 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆43Apr 13, 2025Updated last year
- ☆63May 22, 2026Updated 4 months ago