AI-native Chiplet design flow based on open-source EDA toolchain
☆41Aug 4, 2026Updated this week
Alternatives and similar repositories for Babel
Users that are interested in Babel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆34Feb 2, 2026Updated 6 months ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 3 months ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- ☆26Jul 22, 2026Updated 2 weeks ago
- BP list decoding for polar codes☆14Sep 1, 2023Updated 2 years ago
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆30Jan 25, 2024Updated 2 years ago
- System on Chip verified with UVM/OSVVM/FV☆36Updated this week
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- ☆15Sep 14, 2020Updated 5 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 5 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆21Apr 12, 2026Updated 3 months ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- CMake/GoogleTest/TravisCI/Coveralls/CoverityScan/Doxygen☆10Aug 8, 2019Updated 7 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Analog HDL Design Full-stack Agents☆18Jun 8, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- A Customized ASIC framework for Retro Stuff☆27Updated this week
- ☆18Sep 2, 2020Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆19Feb 27, 2025Updated last year
- ☆35Jul 9, 2025Updated last year
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 9 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 6 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆53Jan 19, 2021Updated 5 years ago
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 7 years ago
- VLSI placement and routing tool☆15Dec 20, 2025Updated 7 months ago
- mojito☆12May 1, 2018Updated 8 years ago
- svlib from http://www.verilab.com/resources/svlib/☆28Jun 2, 2020Updated 6 years ago
- A curated, community-maintained list of ML/LLM research and tools for integrated-circuit design — across the full flow.☆21Updated this week