UnityChip Verification AI-Agent
☆103Mar 19, 2026Updated this week
Alternatives and similar repositories for UCAgent
Users that are interested in UCAgent are comparing it to the libraries listed below
Sorting:
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Feb 25, 2026Updated 3 weeks ago
- TLAi+ Benchmarks☆30Feb 6, 2026Updated last month
- LLM Evaluation Benchmark on Hardware Formal Verification☆40Apr 3, 2025Updated 11 months ago
- This is for uvm_tb_gen☆52Feb 13, 2025Updated last year
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 4 months ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆30Jan 25, 2024Updated 2 years ago
- Specula: A framework for finding deep bugs in system code using TLA+☆104Updated this week
- A framework for building hardware verification platform using software method☆33Dec 24, 2025Updated 2 months ago
- 中国科学院大学-C语言编程-五子棋☆23Nov 29, 2023Updated 2 years ago
- Pick your favorite language to verify your chip.☆79Jan 30, 2026Updated last month
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆26Sep 3, 2024Updated last year
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated 6 months ago
- RISC-V muticycle implementation in VHDL. Core supports multiple peripherals and interruptions using a simple local interrupt controller.☆22Dec 19, 2025Updated 3 months ago
- UCAS大二C语言课程大作业五子棋☆14Jan 1, 2022Updated 4 years ago
- Example SystemVerilog UVM Environment☆10Jun 23, 2015Updated 10 years ago
- Leaderboard of Frontier Models for Program Repair https://repairbench.github.io/☆11Oct 26, 2025Updated 4 months ago
- Scalable Distributed System Model Checking with Specification-Level State Exploration☆28Apr 24, 2024Updated last year
- The first large scale formally verified reasoning dataset for Verilog☆21May 16, 2025Updated 10 months ago
- RISC-V architecture concurrency model litmus tests☆101Jan 21, 2026Updated last month
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated last month
- ☆16Oct 20, 2025Updated 5 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- ucas Network lab. 中国科学院大学计算机网络实验☆49Aug 13, 2018Updated 7 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated 11 months ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 4 years ago
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆47Mar 3, 2024Updated 2 years ago
- Yet another Linux distro for RISC-V.☆13Dec 25, 2025Updated 2 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆32Oct 12, 2025Updated 5 months ago
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 5 years ago
- SBOM-TOOL is a ctl tool that generates software bill of materials (SBOM) for software projects through source code warehouse, code finger…☆13Oct 11, 2025Updated 5 months ago
- [ICLR 2024]: Is Self-Repair a Silver Bullet for Code Generation?☆15May 2, 2024Updated last year
- Vibe Coding A GPGPU via Cursor + Gemini3 Pro☆54Nov 23, 2025Updated 3 months ago
- ☆16Oct 26, 2024Updated last year
- 中国科学院大学-C语言大作业-五子棋AI（wcg班十多名，菜狗一个T T）☆28Mar 4, 2023Updated 3 years ago
- Base repo of a workable zsim on newer version of Ubuntu, with PIN-2.14 binary (the original zSim no longer works)☆14Nov 20, 2022Updated 3 years ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆44Dec 21, 2020Updated 5 years ago
- Encapsulate Xilinx PetaLinux tools 14.04 into docker image☆14Jun 25, 2018Updated 7 years ago