VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
☆36Jul 9, 2026Updated this week
Alternatives and similar repositories for veriflow-cc
Users that are interested in veriflow-cc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL agent team; Harness for Agentic hardware design and verificiation.☆39Updated this week
- Digital HDL Design Full-stack Agents☆165Updated this week
- ☆18Updated this week
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- ☆15Sep 13, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This project is primarily aimed at showcasing an EDA toolchain based on the OpenClaw framework, in which our own research work is also de…☆59Apr 2, 2026Updated 3 months ago
- ☆15Jun 24, 2025Updated last year
- A Claude Code plugin for process management from requirement sorting to delivery☆21Jun 4, 2026Updated last month
- ☆59Updated this week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 8 months ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 4 years ago
- Petri Net Simulator program☆10Nov 27, 2017Updated 8 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Implementation of the PCIe physical layer☆63Jul 11, 2025Updated last year
- 软件无线电，使用FPGA进行正交解调。☆23Feb 18, 2019Updated 7 years ago
- 开放验证平台NutShell Cache验证案例☆12Dec 2, 2025Updated 7 months ago
- zynqmp_cam_isp_demo linux软件项目☆23Dec 18, 2022Updated 3 years ago
- ePIC (Embedded PIC) example: kernel and relocatable loadable app☆14Oct 27, 2023Updated 2 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.☆12Sep 29, 2022Updated 3 years ago
- ☆20May 22, 2026Updated last month
- MegaRAC Open Redfish Framework☆15May 7, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FPGA based Vision Transformer accelerator (Harvard CS205)☆160Feb 11, 2025Updated last year
- This is a Python module for fitting impedance data to electrical models. It uses Lcapy to determine the impedance of arbitrary networks.☆14Jul 23, 2025Updated 11 months ago
- Scripts to automate building linux images for my emulator riscv_em☆16Oct 24, 2023Updated 2 years ago
- ☆17Updated this week
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 7 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆25Feb 16, 2024Updated 2 years ago
- A module to augment the Aux-In functionality of SAAB 93NG's (2002/3+), to add Bluetooth media playback and steering wheel media control s…☆11Aug 17, 2025Updated 10 months ago
- ☆18Jun 29, 2026Updated 2 weeks ago
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Feb 16, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆12Dec 26, 2024Updated last year
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- A standalone userspace Wireguard (Boringtun) implementation built to be as small as possible.☆13Jun 30, 2026Updated 2 weeks ago
- A flexible and scalable development platform for modern FPGA projects.☆45Jul 6, 2026Updated last week
- fpga based nes box☆23Sep 20, 2021Updated 4 years ago