AES-128 hardware implementation
☆34May 4, 2020Updated 6 years ago
Alternatives and similar repositories for aes
Users that are interested in aes are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AES implementation on FPGA☆13Apr 17, 2016Updated 10 years ago
- high level VHDL floating point library for synthesis in fpga☆18Sep 4, 2026Updated 3 weeks ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- This project is a High and Low pass filter designer written in Octave to design and calculate the filter coefficients for a windows sinc …☆15May 3, 2015Updated 11 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆19Jan 28, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 9 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- VHDL implementation of CCSDS123 compression standard☆11Mar 30, 2019Updated 7 years ago
- 基于opencv的树莓派小球平衡控制项目,识别并定位小球在滑轨上的位置,并通过串口发送给stm32f103单片机☆14Jun 21, 2017Updated 9 years ago
- AES implementation in MATLAB☆12Nov 15, 2016Updated 9 years ago
- A VHDL implementation of SipHash☆13Feb 19, 2015Updated 11 years ago
- Design and implementation of a reconfigurable FIR filter in FPGA☆17Sep 26, 2022Updated 4 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- Lecture about FIR filter on an FPGA☆17May 15, 2024Updated 2 years ago
- helpers for qemu irix/solaris userland emulation☆16May 9, 2022Updated 4 years ago
- Senior Design☆12Jan 26, 2025Updated last year
- Simulates gcode from a cnc router. Converts gcode to a .stl or an image in a .png file.☆14Mar 19, 2026Updated 6 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- A bare-metal pure hardware implementation of the Tetris game for FPGA☆21Apr 25, 2017Updated 9 years ago
- ☆12Jun 4, 2021Updated 5 years ago
- Pong game on FPGA Max 10 DE10-Lite, written in VHDL.☆17Oct 14, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Minimal ncurses implementation for use in embedded environments☆12Oct 29, 2017Updated 8 years ago
- USB library for ChipWhisperer devices☆16Jun 12, 2026Updated 3 months ago
- AES-based-on-FPGA developed by verilog.☆22Apr 23, 2020Updated 6 years ago
- SQRL FK33 board files, example designs and scripts.☆22Nov 7, 2022Updated 3 years ago
- Bonfire SoC running on FireAnt FPGA Board☆12Feb 11, 2024Updated 2 years ago
- Running Rust on the (Linux) Litex VexRiscv FPGA SOC☆16Jun 3, 2025Updated last year
- AVR-Bootloader mit Verschlüsselung von Hagen Re☆10Aug 27, 2015Updated 11 years ago
- A system-on-chip project based around Tobias Gubener's TG68k softcore processor☆23Aug 26, 2015Updated 11 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 8 years ago
- Thin Python wrapper around OpenOCD telnet console.☆11May 10, 2019Updated 7 years ago
- OpenCL version of Kaktwoos; Mine cacti with 0xA presses☆10Jun 16, 2022Updated 4 years ago
- DOM Protected Hardware Implementation of AES☆28May 20, 2016Updated 10 years ago
- Verilog RTL Design☆53Sep 4, 2021Updated 5 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆463Dec 29, 2025Updated 8 months ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆17Dec 8, 2020Updated 5 years ago