Alternatives and similar repositories for aes

Users that are interested in aes are comparing it to the libraries listed below

• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 11 months ago
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆123Updated 4 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆132Updated last year
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆123Updated 5 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆148Updated 5 months ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆282Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆171Updated 5 years ago
• timvideos / litex-buildenv
  An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
  ☆219Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆157Updated 7 years ago
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆196Updated last month
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆261Updated 6 years ago
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆39Updated last year
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆310Updated 2 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆84Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• olofk / corescore
  CoreScore
  ☆168Updated last week
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated 2 weeks ago
• olofk / vidbo
  Virtual Development Board
  ☆64Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆89Updated 6 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 3 weeks ago
• ldoolitt / vhd2vl
  ☆137Updated 11 months ago
• ultraembedded / FPGAmp
  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
  ☆285Updated 5 years ago