gzzyyxh / QuafuLinks
A small SoC with a pipeline 32-bit RISC-V CPU.
☆66Updated 3 years ago
Alternatives and similar repositories for Quafu
Users that are interested in Quafu are comparing it to the libraries listed below
Sorting:
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆91Updated 2 months ago
- ☆64Updated 3 years ago
- ☆87Updated last month
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆44Updated 2 years ago
- Pick your favorite language to verify your chip.☆74Updated this week
- ☆19Updated 2 years ago
- ☆47Updated 3 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆72Updated 2 years ago
- ☆37Updated 7 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- ☆68Updated 10 months ago
- Modern co-simulation framework for RISC-V CPUs☆165Updated this week
- ☆30Updated 9 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆180Updated 4 years ago
- ☆40Updated 2 years ago
- XiangShan Frontend Develop Environment☆68Updated last week
- ☆33Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Updated last month
- ☆67Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆192Updated last year
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆156Updated 6 years ago
- 一生一芯的信息发布和内容网站☆135Updated 2 years ago