Alternatives and similar repositories for Quafu:

Users that are interested in Quafu are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆79Updated last week
• OSCPU / yosys-sta
  ☆53Updated last month
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆57Updated 2 years ago
• CherrySprings / CherrySprings
  ☆17Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆140Updated 6 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆56Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆139Updated 4 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆50Updated 6 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆138Updated 2 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆113Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 7 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• tastynoob / ritter-soc
  a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
  ☆22Updated last year
• OpenXiangShan / XS-Verilog-Library
  ☆38Updated 2 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• OSCPU / chisel-playground
  ☆59Updated 2 weeks ago
• USTC-System-Courses / CECS-Lab
  ☆31Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆102Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆133Updated 5 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆25Updated 2 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆89Updated 8 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year