gzzyyxh / Quafu
A small SoC with a pipeline 32-bit RISC-V CPU.
☆62Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for Quafu
- ☆76Updated 2 months ago
- ☆43Updated 4 months ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆54Updated last year
- "aura" my super-scalar O3 cpu core☆24Updated 5 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆46Updated 2 years ago
- ☆63Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 2 years ago
- ☆16Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆116Updated last month
- ☆36Updated 2 years ago
- ☆60Updated 3 months ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆135Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆36Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 8 months ago
- Modern co-simulation framework for RISC-V CPUs☆118Updated this week
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆121Updated 4 months ago
- ☆56Updated 4 months ago
- ☆35Updated 6 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆20Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 8 months ago
- AXI协议规范中文翻译版☆132Updated 2 years ago
- ☆62Updated 3 months ago
- Pick your favorite language to verify your chip.☆31Updated this week
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆20Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 7 months ago
- CPU Design Based on RISCV ISA☆76Updated 5 months ago
- ☆52Updated last year