gzzyyxh / QuafuView external linksLinks
A small SoC with a pipeline 32-bit RISC-V CPU.
☆66Jun 1, 2022Updated 3 years ago
Alternatives and similar repositories for Quafu
Users that are interested in Quafu are comparing it to the libraries listed below
Sorting:
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Jun 3, 2022Updated 3 years ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 2 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆14Sep 7, 2021Updated 4 years ago
- a compiler for CSC-Compiler-2022☆13Aug 22, 2022Updated 3 years ago
- 遵循GPL-2.0规则，将phoenix kernel部分开源☆13Sep 15, 2022Updated 3 years ago
- XFS readonly driver for Windows☆15Jun 30, 2012Updated 13 years ago
- 基于FPGA实现用户态中断硬件机制与优化操作系统内核☆10Apr 1, 2025Updated 10 months ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 5 months ago
- Isle FPGA Computer☆71Jan 22, 2026Updated 3 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- Remote desktop protocol (RDP) server—mirror of https://github.com/neutrinolabs/xrdp.git☆13Updated this week
- fpga verilog risc-v rv32i cpu☆14Apr 18, 2023Updated 2 years ago
- A simple 5-stage Pipeline RISC-V core☆19Jun 8, 2021Updated 4 years ago
- ☆18May 31, 2022Updated 3 years ago
- ☆21May 26, 2025Updated 8 months ago
- ☆37Nov 11, 2018Updated 7 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆37Jan 26, 2022Updated 4 years ago
- ☆18Jul 5, 2023Updated 2 years ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆318Updated this week
- "Very low cost, tiny (USB thumb size) FPGA board. 1st board with Efinix Trion FPGA and comes with Efinity IDE Solder or unsoldered versio…☆25Nov 11, 2019Updated 6 years ago
- 这是武汉大学WHU 计算机组成与设计 RISC-V CPU 流水线设计，包括Modelsim仿真测试，vivado下FPGA(NEXYS A7)测试。☆31May 21, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Feb 3, 2026Updated last week
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Jan 1, 2022Updated 4 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 4 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- A project for learning RISC-V architecture purpose☆26Nov 9, 2023Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- Introduction to Computer Systems (II), Spring 2021☆52Jul 3, 2021Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆120Dec 17, 2023Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆31Aug 28, 2025Updated 5 months ago
- Minimal implementation of Raybox HDL ray caster concept☆26Nov 24, 2025Updated 2 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆33Jun 30, 2021Updated 4 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆85Nov 26, 2021Updated 4 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆122Aug 27, 2024Updated last year