Alternatives and similar repositories for Quafu

Users that are interested in Quafu are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆86Updated last month
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OSCPU / yosys-sta
  ☆64Updated last month
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆62Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆66Updated 2 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated 9 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated last week
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆23Updated last week
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆40Updated last year
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 9 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆23Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆59Updated 3 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆28Updated 2 years ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 6 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated 8 months ago
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆60Updated last year
• tastynoob / ritter-soc
  a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
  ☆23Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆136Updated 11 months ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆120Updated 2 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆150Updated 2 years ago
• EECS150 / fpga_labs_sp22
  ☆30Updated 3 years ago