gzzyyxh / QuafuLinks
A small SoC with a pipeline 32-bit RISC-V CPU.
☆65Updated 3 years ago
Alternatives and similar repositories for Quafu
Users that are interested in Quafu are comparing it to the libraries listed below
Sorting:
- ☆86Updated last month
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- ☆18Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 10 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆64Updated 2 years ago
- ☆72Updated 2 months ago
- ☆66Updated 10 months ago
- ☆68Updated 2 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆62Updated 2 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆29Updated 2 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆121Updated 2 years ago
- ☆36Updated 6 years ago
- Pick your favorite language to verify your chip.☆50Updated last week
- AXI协议规范中文翻译版☆152Updated 2 years ago
- ☆42Updated 3 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- ☆22Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆171Updated 8 months ago
- ☆67Updated 4 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A RISC-V RV32I ISA Single Cycle CPU☆24Updated last month
- Modern co-simulation framework for RISC-V CPUs☆146Updated this week
- ☆24Updated 2 months ago
- commit rtl and build cosim env☆15Updated last year
- HYF's high quality verilog codes☆13Updated 5 months ago