Alternatives and similar repositories for SampleCPU

Users that are interested in SampleCPU are comparing it to the libraries listed below

• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆36Updated 4 years ago
• TrivialCompiler / TrivialCompiler
  A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.
  ☆146Updated 4 years ago
• Pengwei-Jin / AICS-homework
  智能计算系统作业（2021年）
  ☆53Updated 4 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 4 years ago
• CQU-CS-LABs / CO-lab-docs-CQU
  重庆大学硬件综合设计课程实验文档
  ☆43Updated 6 months ago
• cyyself / sockraw-udp
  在Linux下使用PF_PACKET的Raw Socket实现从以太网到UDP的封装，并支持IPv4 Fragment，重大18计卓班的计网Project
  ☆32Updated 4 years ago
• LuoXukun / AI-homework
  智能计算系统作业
  ☆148Updated 2 years ago
• HITSZ-CDP / cdp-tests
  《计算机设计与实践》测试框架
  ☆17Updated 3 years ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆52Updated 4 years ago
• pinchenjohnny / Distributed_System_Architecture
  高级计算机体系结构2020，吴俊敏老师，中科大研究生课程
  ☆73Updated 2 years ago
• CherryYang05 / OpenMIPS_CPU
  基于龙芯 OpenMIPS 实现一个具有 89 条指令的五级流水 CPU，使用 Verilog 语言，使用哈佛结构，包括逻辑移位指令、乘除法指令、加载存储指令、转移指令、协处理器访问指令以及异常相关在内的共89条指令。能够处理数据相关，包含流水线暂停以及延迟槽
  ☆20Updated 5 years ago
• No-SF-Work / miniSysY-tutorial
  BUAASE2019级的编译实验的实验指导与实验安排
  ☆118Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆47Updated 3 years ago
• kobayashi-compiler / kobayashi-compiler
  An optimizing compiler targeting armv7 and risc-v32
  ☆63Updated last year
• oscomp / testsuits-for-oskernel
  ☆146Updated 5 months ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• oscomp / 2021oscomp-best-kernel-design-impl
  2021年OS比赛获奖赛题（文档/代码开源），可用于2022年参赛同学的学习和提高
  ☆48Updated 4 years ago
• fluctlight001 / Nova132
  A classic five stage pipelined processor
  ☆13Updated last year
• 14010007517 / 2020NSCSCC
  Chongqing University 2020 NSCSCC
  ☆29Updated 5 years ago
• GrapeLemonade / useless-compiler
  北航编译原理 2020 课设 / BUAA Compiler 2020 / Naive speedrun useless compiler
  ☆14Updated 3 years ago
• LearningOS / rCore-Tutorial-Code-2023S
  Let's write an OS which can run on RISC-V in Rust from scratch!
  ☆16Updated 2 years ago
• LeiWang1999 / AICS-Course
  《智能计算系统 AI Computing Systems》习题答案、实验答案、课程笔记
  ☆213Updated 3 years ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆30Updated last year
• SYSU-SCC / yatcpu-docs
  Documentation for YatCPU
  ☆54Updated 2 years ago
• MAdrid1011 / Zircon
  ☆30Updated last year
• cocodery / SysYCompiler
  a compiler for CSC-Compiler-2022
  ☆13Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• roife / BUAA-CO
  Pipelined MIPS CPU（course assignment for BUAA-Computer-Organization）
  ☆22Updated 4 years ago