mbaykenar / mpw7_yonga_socLinks
Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C
☆17Updated 2 years ago
Alternatives and similar repositories for mpw7_yonga_soc
Users that are interested in mpw7_yonga_soc are comparing it to the libraries listed below
Sorting:
- 64-bit RISC-V processor☆16Updated 2 years ago
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆20Updated 2 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆14Updated last year
- SystemVerilog Tutorial☆159Updated 2 months ago
- Basic RISC-V Test SoC☆137Updated 6 years ago
- Verilog HDL files☆146Updated last year
- ☆95Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- I2C slave Verilog Design and TestBench☆25Updated 6 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆181Updated 3 weeks ago
- https://caravel-user-project.readthedocs.io☆210Updated 4 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆105Updated 9 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆133Updated last month
- Arduino compatible Risc-V Based SOC☆153Updated last year
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆172Updated this week
- A demo system for Ibex including debug support and some peripherals☆73Updated last month
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- ☆12Updated 3 months ago
- Simple 8-bit UART realization on Verilog HDL.☆107Updated last year
- FPGA Logic Analyzer and GUI☆134Updated 2 years ago
- Implementation of RISC-V RV32I☆19Updated 2 years ago
- Verilog implementation of a RISC-V core☆121Updated 6 years ago
- A simple implementation of a UART modem in Verilog.☆142Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆132Updated last year
- Lecture about FIR filter on an FPGA☆12Updated last year
- This repo provide an index of VLSI content creators and their materials☆152Updated 10 months ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆34Updated 3 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆161Updated 2 years ago