Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C
☆22Nov 21, 2022Updated 3 years ago
Alternatives and similar repositories for mpw7_yonga_soc
Users that are interested in mpw7_yonga_soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This course is given in ERCIYES UNIVERSITY for Spring 2022-2023 semester as a fourth grade lecture. You can find lecture notes, RISC-V as…☆19Jun 20, 2023Updated 2 years ago
- Raspberry Pi CAN extension board☆14Sep 24, 2023Updated 2 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Nov 19, 2023Updated 2 years ago
- A testbench for an axi lite custom IP☆24Dec 18, 2014Updated 11 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆51Dec 18, 2025Updated 4 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 3 years ago
- FPGA implementation of the hector_slam algorithm using only lidar data☆10Jul 3, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- PYNQ-T9 repo. Use antminer t9 (with 1GbE) as PYNQ devboard.☆14Nov 7, 2024Updated last year
- Histogram Equalization Implementation by MATLAB☆12Nov 15, 2016Updated 9 years ago
- Play for Windows☆67Apr 14, 2023Updated 3 years ago
- ☆21Mar 30, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- courses to learn VHDL☆17Mar 14, 2022Updated 4 years ago
- Verilog HDL code and Finite State Machine (FSM) for a simple ATM☆12Jul 26, 2020Updated 5 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Resources & Notes for learning Norwegian Language☆25Aug 26, 2025Updated 8 months ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Open-source version of SpaceWire-to-GigabitEther using ZestET1☆27Feb 15, 2016Updated 10 years ago
- Dump/Steal and decrypt Google Chrome passwords (Windows)☆20Jun 16, 2021Updated 4 years ago
- ☆14Apr 28, 2015Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- verilog modules☆15May 4, 2020Updated 6 years ago
- Package demo for ROS navigation in Gazebo usingo Pioneer 3AT.☆22May 8, 2020Updated 6 years ago
- Li-Ion battery test bench monitor with web user interface over TCP/IP connection.☆24Aug 5, 2019Updated 6 years ago
- RISC-V RV32IM cpu circuit in Logisim Evolution.☆27Jun 9, 2021Updated 4 years ago
- Find mDNS Terminal with Android☆13Feb 5, 2023Updated 3 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- Minimal kernel for cortex m based microcontrollers.☆11Jun 14, 2025Updated 10 months ago
- SoC Based on ARM Cortex-M3☆38May 16, 2025Updated 11 months ago
- ☆21Jun 17, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆38Mar 18, 2023Updated 3 years ago
- 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.☆214Jun 5, 2021Updated 4 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆203Apr 3, 2026Updated last month
- This repository includes the AGV-OTA ROS Noetic packages.☆26May 30, 2024Updated last year
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 3 years ago
- Implementation of Histogram Equalization, Logarithmic Mapping, Image Rotation, Gaussian Averaging Filter and Median Filter. Histogram eq…☆17Sep 20, 2016Updated 9 years ago
- MPU6050 interface for fpga☆11May 9, 2020Updated 5 years ago