tomverbeure / ecp5_jtagLinks
Use ECP5 JTAG port to interact with user design
☆28Updated 3 years ago
Alternatives and similar repositories for ecp5_jtag
Users that are interested in ecp5_jtag are comparing it to the libraries listed below
Sorting:
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆21Updated this week
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆65Updated 8 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- ☆45Updated 2 years ago
- IceCore Ice40 HX based modular core☆46Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Wishbone interconnect utilities☆41Updated 3 months ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- I want to learn [n]Migen.☆41Updated 5 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆30Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆48Updated this week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆92Updated 8 months ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- Portable HyperRAM controller☆55Updated 5 months ago
- UPduino☆27Updated 5 years ago
- Nitro USB FPGA core☆84Updated last year
- A configurable USB 2.0 device core☆31Updated 4 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆39Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆15Updated 3 years ago