tomverbeure / ecp5_jtagLinks
Use ECP5 JTAG port to interact with user design
☆29Updated 3 years ago
Alternatives and similar repositories for ecp5_jtag
Users that are interested in ecp5_jtag are comparing it to the libraries listed below
Sorting:
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆22Updated this week
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated 3 weeks ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 2 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- IceCore Ice40 HX based modular core☆46Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆44Updated 4 months ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆28Updated 6 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆29Updated 11 months ago
- ☆45Updated 2 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆15Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- assorted library of utility cores for amaranth HDL☆92Updated 9 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- Miscellaneous ULX3S examples (advanced)☆78Updated last week
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- I want to learn [n]Migen.☆42Updated 5 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- ☆22Updated 3 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆29Updated last year