embed-me / vunit-mode
A simple Emacs minor mode for VUnit
☆12Updated last year
Alternatives and similar repositories for vunit-mode:
Users that are interested in vunit-mode are comparing it to the libraries listed below
- Emacs Verilog Tree-sitter Major-mode☆11Updated last month
- VHDL Extensions for Emacs☆35Updated last month
- Verilog Extensions for Emacs☆60Updated last month
- fpga.el - FPGA & ASIC Utils for Emacs☆22Updated last month
- VHDL String Formatting Library☆24Updated 9 months ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- VHDL grammar for tree-sitter☆31Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated 2 weeks ago
- I2C models for cocotb☆29Updated 10 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 11 months ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆21Updated last week
- VHDL related news.☆25Updated this week
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆52Updated 5 months ago
- Library of reusable VHDL components☆27Updated 11 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆52Updated last week
- CLI for WaveDrom☆61Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆54Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆42Updated 2 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆26Updated last month
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 4 years ago
- OSVVM Documentation☆33Updated this week
- VHDL dependency analyzer☆23Updated 4 years ago
- Hardware CD/CI and Development Containers 🚢☆10Updated 2 years ago
- Tools for Verilog HDL development.☆10Updated 12 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆43Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 weeks ago
- Streaming based VHDL parser.☆81Updated 7 months ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated last year
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago