Alternatives and similar repositories for vunit-mode

Users that are interested in vunit-mode are comparing it to the libraries listed below

• gmlarumbe / vhdl-ext
  VHDL Extensions for Emacs
  ☆35Updated last week
• gmlarumbe / verilog-ts-mode
  Emacs Verilog Tree-sitter Major-mode
  ☆12Updated last week
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated this week
• gmlarumbe / fpga
  fpga.el - FPGA & ASIC Utils for Emacs
  ☆22Updated 3 weeks ago
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• jwwebbopen / SystemVerilogTools
  Tools for SystemVerilog development.
  ☆15Updated 7 years ago
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆272Updated 2 weeks ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• jwwebbopen / VerilogTools
  Tools for Verilog HDL development.
  ☆10Updated 13 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆35Updated 3 weeks ago
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆29Updated 7 months ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆21Updated last month
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆26Updated 2 weeks ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated last month
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆81Updated 5 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆35Updated 4 months ago
• Mluckydwyer / hw-ci
  Hardware CD/CI and Development Containers 🚢
  ☆10Updated 3 years ago
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆36Updated 8 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆95Updated 3 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆55Updated last month
• Remillard / VHDL-Mode
  A package for Sublime Text that aids coding in the VHDL language.
  ☆41Updated last year
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆56Updated 2 years ago
• miree / gvi
  GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
  ☆14Updated 4 months ago