Alternatives and similar repositories for vunit-mode

Users that are interested in vunit-mode are comparing it to the libraries listed below

• gmlarumbe / vhdl-ext
  VHDL Extensions for Emacs
  ☆35Updated 2 months ago
• gmlarumbe / verilog-ts-mode
  Emacs Verilog Tree-sitter Major-mode
  ☆11Updated 4 months ago
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated 2 months ago
• gmlarumbe / fpga
  fpga.el - FPGA & ASIC Utils for Emacs
  ☆22Updated 2 months ago
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆281Updated 3 weeks ago
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆32Updated 2 years ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 8 months ago
• miree / gvi
  GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
  ☆16Updated 9 months ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆40Updated 5 months ago
• Remillard / VHDL-Mode
  A package for Sublime Text that aids coding in the VHDL language.
  ☆42Updated 2 years ago
• jwwebbopen / SystemVerilogTools
  Tools for SystemVerilog development.
  ☆15Updated 8 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆66Updated last year
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆52Updated 2 months ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 6 years ago
• VHDL / news
  VHDL related news.
  ☆27Updated this week
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆60Updated last week
• kevinpt / symbolator
  HDL symbol generator
  ☆201Updated 3 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆57Updated 3 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆30Updated last year
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 3 weeks ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆74Updated 4 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆27Updated last year
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆62Updated 3 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆74Updated last year
• byu-cpe / BYU-Computing-Tutorials
  Collection of tutorials from the BYU Computer Engineering Group
  ☆23Updated 5 years ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆88Updated this week