Alternatives and similar repositories for vunit-mode

Users that are interested in vunit-mode are comparing it to the libraries listed below

• gmlarumbe / vhdl-ext
  VHDL Extensions for Emacs
  ☆35Updated last month
• gmlarumbe / verilog-ts-mode
  Emacs Verilog Tree-sitter Major-mode
  ☆11Updated last month
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated last month
• gmlarumbe / fpga
  fpga.el - FPGA & ASIC Utils for Emacs
  ☆22Updated last month
• miree / gvi
  GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
  ☆16Updated 6 months ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆30Updated 9 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• VHDL / news
  VHDL related news.
  ☆26Updated this week
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆101Updated 5 months ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆39Updated 3 weeks ago
• jwwebbopen / VerilogTools
  Tools for Verilog HDL development.
  ☆10Updated 13 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆276Updated 3 months ago
• g2384 / VHDLFormatter
  VHDL formatter web online written in typescript
  ☆57Updated 2 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆28Updated 3 months ago
• csantosb / vhdl-tools
  Easier navigation of VHDL sources
  ☆12Updated 5 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆38Updated 2 months ago
• Remillard / VHDL-Mode
  A package for Sublime Text that aids coding in the VHDL language.
  ☆42Updated 2 years ago
• jwwebbopen / SystemVerilogTools
  Tools for SystemVerilog development.
  ☆15Updated 7 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated 2 years ago
• wavedrom / cli
  CLI for WaveDrom
  ☆63Updated last year
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆82Updated 5 years ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆25Updated 8 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆56Updated 3 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆63Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year