Zhikharev / selenLinks
SoC based on RISC V ISA
☆10Updated 3 years ago
Alternatives and similar repositories for selen
Users that are interested in selen are comparing it to the libraries listed below
Sorting:
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Updated 10 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 5 years ago
- A mock framework for use with SVUnit☆18Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 5 months ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago
- ☆23Updated 8 months ago
- AXI X-Bar☆19Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆31Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- UVM Clock and Reset Agent☆13Updated 8 years ago
- Connecting SystemC with SystemVerilog☆41Updated 13 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆18Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 5 months ago
- UVM VIP architecture generator☆20Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Updated 5 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆35Updated 10 years ago
- A CSV file parser, written in SystemVerilog☆26Updated 9 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- ☆13Updated 8 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- make your verilog DUT test more smart☆22Updated 9 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Verification IP for UART protocol☆20Updated 5 years ago