Zhikharev / selen
SoC based on RISC V ISA
☆10Updated 2 years ago
Alternatives and similar repositories for selen:
Users that are interested in selen are comparing it to the libraries listed below
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 4 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 9 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆16Updated 9 months ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆29Updated 12 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆27Updated last month
- Open-Source Framework for Co-Emulation☆11Updated 3 years ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- Generate UVM testbench framework template files with Python 3☆25Updated 5 years ago
- Systemverilog DPI-C call Python function☆22Updated 3 years ago
- Connecting SystemC with SystemVerilog☆37Updated 12 years ago
- YosysHQ SVA AXI Properties☆37Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆15Updated 4 years ago
- UVM Python Verification Agents Library☆14Updated 3 years ago
- ☆14Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- A mock framework for use with SVUnit☆15Updated last year
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆21Updated 9 years ago
- ☆12Updated 7 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Contains commonly used UVM components (agents, environments and tests).☆26Updated 6 years ago
- ☆37Updated 3 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆35Updated 7 months ago
- SystemVerilog Design Patterns☆26Updated 9 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Doxygen with verilog support☆37Updated 5 years ago