Zhikharev / selen

Related projects ⓘ

Alternatives and complementary repositories for selen

• seabeam / yuu_clock
  UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
  ☆10Updated 4 years ago
• amiq-consulting / cagt
  Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …
  ☆11Updated 9 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆25Updated 3 weeks ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆36Updated 12 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆15Updated last year
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆15Updated 6 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆32Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆29Updated 3 years ago
• luuvish / system-verilog-patterns
  SystemVerilog Design Patterns
  ☆26Updated 9 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆57Updated 5 months ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆21Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆26Updated 9 years ago
• shady831213 / jarvisuk
  Just A Really Very Impressive Systemverilog UVM Kit
  ☆15Updated 3 years ago
• amiq-consulting / amiq_ofc
  Open-Source Framework for Co-Emulation
  ☆11Updated 3 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆26Updated 6 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆15Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆43Updated 3 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆17Updated 4 months ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆54Updated 3 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆30Updated 4 years ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆34Updated 5 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆17Updated 5 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆17Updated 4 years ago