samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
☆16Updated 5 years ago
Alternatives and similar repositories for MAXVY_MIPI_I3C_Basic_Master_Controller_IP
Users that are interested in MAXVY_MIPI_I3C_Basic_Master_Controller_IP are comparing it to the libraries listed below
Sorting:
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Implementation of the PCIe physical layer☆39Updated 3 months ago
- ☆16Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- ☆36Updated 9 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- ☆21Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- System on Chip verified with UVM/OSVVM/FV☆25Updated last week
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- ☆15Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Must-have verilog systemverilog modules☆34Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- ☆19Updated 2 years ago
- ☆25Updated 4 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 6 years ago
- I2C controller core☆39Updated 2 years ago