Alternatives and similar repositories for MAXVY_MIPI_I3C_Basic_Master_Controller_IP

Users that are interested in MAXVY_MIPI_I3C_Basic_Master_Controller_IP are comparing it to the libraries listed below

• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 6 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆67Updated 4 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆59Updated 4 months ago
• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆32Updated this week
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆46Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆72Updated 8 years ago
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆45Updated 8 years ago
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆28Updated 13 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 8 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆28Updated 8 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆97Updated 5 years ago
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆29Updated 7 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆88Updated last year