samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IPLinks
It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
☆19Updated 5 years ago
Alternatives and similar repositories for MAXVY_MIPI_I3C_Basic_Master_Controller_IP
Users that are interested in MAXVY_MIPI_I3C_Basic_Master_Controller_IP are comparing it to the libraries listed below
Sorting:
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- SDRAM controller with AXI4 interface☆99Updated 6 years ago
- ☆38Updated 10 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Video Stream Scaler☆40Updated 11 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- UART -> AXI Bridge☆68Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- AXI Interconnect☆54Updated 4 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- An 8 input interrupt controller written in Verilog.☆28Updated 13 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆58Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆99Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆94Updated last year
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 6 years ago
- USB 2.0 Device IP Core☆73Updated 8 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- ☆26Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆81Updated last year
- DMA Hardware Description with Verilog☆18Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago