samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IPLinks
It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
☆18Updated 5 years ago
Alternatives and similar repositories for MAXVY_MIPI_I3C_Basic_Master_Controller_IP
Users that are interested in MAXVY_MIPI_I3C_Basic_Master_Controller_IP are comparing it to the libraries listed below
Sorting:
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆130Updated 5 years ago
- I2C controller core☆46Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- ☆38Updated 10 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Implementation of the PCIe physical layer☆50Updated 3 months ago
- ☆25Updated 3 months ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Video Stream Scaler☆40Updated 11 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- USB 2.0 Device IP Core☆71Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 6 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- System on Chip verified with UVM/OSVVM/FV☆32Updated 5 months ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆29Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago