Alternatives and similar repositories for i3c-slave-design:

Users that are interested in i3c-slave-design are comparing it to the libraries listed below

• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 2 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆94Updated 3 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆83Updated 8 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆109Updated 5 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆180Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆142Updated 2 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆90Updated 7 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆125Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆105Updated 10 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆48Updated 5 years ago
• wudayemen / gen_apb_file
  ☆66Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆84Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆61Updated 2 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆31Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆88Updated 4 years ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆149Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆125Updated 5 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆137Updated 7 months ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆115Updated 3 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆81Updated 7 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆68Updated 3 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆55Updated 7 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• BitOpenFPGA / arl
  lists of most popular repositories for most favoured programming languages (according to StackOverflow)
  ☆77Updated 4 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆66Updated 5 years ago
• freecores / i2c
  I2C controller core
  ☆37Updated 2 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 4 years ago