Alternatives and similar repositories for i3c-slave-design

Users that are interested in i3c-slave-design are comparing it to the libraries listed below

• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆122Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆100Updated 3 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆81Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆92Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆88Updated last year
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆66Updated 7 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆201Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆74Updated 2 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆268Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated 2 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• wudayemen / gen_apb_file
  ☆67Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆163Updated 11 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆98Updated 7 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 6 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆145Updated 10 months ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆199Updated last year
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆85Updated last month
• freecores / i2c
  I2C controller core
  ☆39Updated 2 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆128Updated 10 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆53Updated 9 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆96Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆134Updated 2 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆333Updated last year