NXP / i3c-slave-designLinks
MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
☆132Updated 5 years ago
Alternatives and similar repositories for i3c-slave-design
Users that are interested in i3c-slave-design are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- I2C controller core☆47Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆158Updated 9 months ago
- AHB3-Lite Interconnect☆104Updated last year
- OpenXuantie - OpenE902 Core☆163Updated last year
- USB 2.0 Device IP Core☆72Updated 8 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- ☆97Updated 3 months ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- AMBA bus generator including AXI, AHB, and APB☆114Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆19Updated 5 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- Verilog SPI master and slave☆62Updated 9 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆98Updated last year
- SPI Slave for FPGA in Verilog and VHDL☆216Updated last year
- Ethernet 10GE MAC☆46Updated 11 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Verilog UART☆186Updated 12 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- ☆74Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- Basic RISC-V Test SoC☆162Updated 6 years ago
- Verilog digital signal processing components☆159Updated 3 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago