barabanshek / Dagger
HW/SW co-designed end-host RPC stack
☆20Updated 3 years ago
Alternatives and similar repositories for Dagger:
Users that are interested in Dagger are comparing it to the libraries listed below
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆49Updated 8 months ago
- A Cycle-level simulator for M2NDP☆26Updated 4 months ago
- Modifications to GEM5 for running kernel bypass networking. (DPDK)☆15Updated last year
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆10Updated 4 months ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆24Updated 3 weeks ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆21Updated 6 years ago
- A Full-System Simulator for CXL-Based SSD Memory System☆19Updated 4 months ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- A Programmable Hardware Architecture for Network Transport Logic☆35Updated 3 years ago
- ☆14Updated 2 years ago
- ☆25Updated last year
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆26Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆16Updated last year
- this is a repository based on gem5 and aims to be modified for CXL☆21Updated last year
- ☆25Updated 3 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆22Updated 3 years ago
- A Multiplatform benchmark designed to provide holistic, detailed and close-to-hardware view of memory system performance with family of b…☆32Updated 3 weeks ago
- ☆66Updated 4 years ago
- Pin based tool for simulation of rack-scale disaggregated memory systems☆18Updated last month
- Gem5 with PCI Express integrated.☆17Updated 6 years ago
- Clio, ASPLOS'22.☆73Updated 3 years ago
- This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memo…☆44Updated 7 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- ☆25Updated 5 years ago
- 3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit (MICRO 2022)☆12Updated last year