mohaghasemzadeh / ReBNetLinks
Residual Binarized Neural Network
☆43Updated 7 years ago
Alternatives and similar repositories for ReBNet
Users that are interested in ReBNet are comparing it to the libraries listed below
Sorting:
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92Updated 6 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆91Updated 7 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆115Updated 8 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Updated 4 years ago
- ☆64Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆96Updated 4 years ago
- ☆91Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆226Updated 6 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- The second place winner for DAC-SDC 2020☆99Updated 3 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- ☆71Updated 5 years ago
- DAC System Design Contest 2020☆29Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- ☆32Updated 6 years ago
- Caffe to VHDL☆68Updated 5 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆282Updated 6 years ago
- ☆72Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs (FPGA'17)☆311Updated 5 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆39Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- pytorch fixed point training tool/framework☆34Updated 5 years ago
- Design contest for DAC 2018☆17Updated 7 years ago