UCLA-VAST / HT-Deflate-FPGALinks
☆15Updated 3 years ago
Alternatives and similar repositories for HT-Deflate-FPGA
Users that are interested in HT-Deflate-FPGA are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Ethernet switch implementation written in Verilog☆56Updated 2 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- ☆29Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- corundum work on vu13p☆22Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- ☆79Updated 11 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- ☆28Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆54Updated 2 years ago
- ☆13Updated 8 years ago
- ☆34Updated 3 years ago
- ☆26Updated 4 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- CNN accelerator☆28Updated 8 years ago
- ☆70Updated 4 years ago
- ☆31Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated 3 weeks ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 4 months ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago