UCLA-VAST / HT-Deflate-FPGA
☆14Updated 2 years ago
Alternatives and similar repositories for HT-Deflate-FPGA:
Users that are interested in HT-Deflate-FPGA are comparing it to the libraries listed below
- ☆24Updated 5 years ago
- ☆25Updated 11 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆15Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- corundum work on vu13p☆18Updated last year
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆23Updated 6 months ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆18Updated 9 years ago
- HLS code for Network on Chip (NoC)☆16Updated 4 years ago
- ☆22Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- Ethernet switch implementation written in Verilog☆43Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆50Updated 3 years ago
- ☆70Updated 10 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆20Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆22Updated last year
- ☆25Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 4 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago