The Design and Implementation of a Pulse Compression Filter on an FPGA.
☆34Aug 7, 2021Updated 4 years ago
Alternatives and similar repositories for ELEC5882
Users that are interested in ELEC5882 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Miniature 8GHz FMCW Radar☆12Mar 29, 2016Updated 10 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆39Oct 4, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- FMCW Radar verilog project☆35Jun 15, 2020Updated 6 years ago
- An inserted spectrum analyzer based on Zynq-7000, which uses scheme for FPGA+ARM standalone.☆27Apr 30, 2023Updated 3 years ago
- ☆140May 4, 2026Updated last month
- This repository contains FPGA/HDL demonstrations several beamforming and radar designs. Simulink models and MATLAB reference code are pro…☆82Jul 26, 2023Updated 2 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 5 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取…☆31Nov 9, 2015Updated 10 years ago
- 使用Cordic算法函数运算，在资源受限的设备上运行（如资源较少的FPGA、嵌 入式MCU），避免了浮点运算、乘法、除法，只用移位和加法函数的计算。☆14Mar 22, 2024Updated 2 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- A simple FMCW radar works on 5.8GHz☆16Feb 10, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆24Aug 26, 2017Updated 8 years ago
- 使用DDS芯片AD9914产生线性扫频信号☆12Dec 9, 2020Updated 5 years ago
- image processing based FPGA☆119Sep 2, 2021Updated 4 years ago
- UESTC-雷达信号产生与处理的设计与验证☆19Jun 6, 2019Updated 7 years ago
- ☆17Sep 6, 2024Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- This is use FPGA of Xilinx ZYNQ-7000 ZC702☆16Jul 2, 2017Updated 8 years ago
- 组合导航-汽车航位推算☆11Feb 19, 2023Updated 3 years ago
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Codes of different calibration routines: IMU vs CAMERA, CAMERA vs LASER, Ground truth camera vs earth's cs☆15Jan 28, 2014Updated 12 years ago
- ☆13Nov 13, 2022Updated 3 years ago
- Public repository of the data, scripts and methodology presented in the paper "Towards On-Board SAR Processing with FPGA Accelerators and…☆13Apr 12, 2023Updated 3 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆124Updated this week
- FIR filter implementation☆29Mar 19, 2020Updated 6 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 8 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Programmable multichannel ADPCM decoder for FPGA☆26Dec 28, 2020Updated 5 years ago
- HDL and software samples for interfacing the XEM7320 with various SYZYGY peripherals.☆13Nov 14, 2019Updated 6 years ago
- ☆11May 24, 2019Updated 7 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 给定ARM Cortex-M3的软核，扩展周围的AMBA总线以及基本外设，完成在上面的汇编以及C语言的执行☆19Aug 26, 2019Updated 6 years ago
- SGMII☆14Jul 17, 2014Updated 11 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆44Jun 22, 2021Updated 4 years ago