The Design and Implementation of a Pulse Compression Filter on an FPGA.
☆37Aug 7, 2021Updated 5 years ago
Alternatives and similar repositories for ELEC5882
Users that are interested in ELEC5882 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 从上位机采用UART或以太网将位流文件烧写到片外Flash中,利用Xilinx FPGA的Multiboot特性,进行OTA(over the air)在线升级。如升级失败,可以回到原来的位流文件。☆13Dec 7, 2023Updated 2 years ago
- Implementation of the Xilinx FFT IP using a UART packetised data stream☆13Jul 24, 2022Updated 4 years ago
- Verilog 8b10b encoder/decoder☆12Mar 11, 2025Updated last year
- A Constant False Alarm Rate Processor Generator☆11Apr 13, 2023Updated 3 years ago
- This repository contains FPGA/HDL demonstrations several beamforming and radar designs. Simulink models and MATLAB reference code are pro…☆87Jul 26, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A simple FMCW radar works on 5.8GHz☆16Feb 10, 2019Updated 7 years ago
- LLM-Aided FPGA Design and Debug Flow☆43Aug 1, 2025Updated last year
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- My code repositry for common use.☆23Dec 31, 2021Updated 4 years ago
- An inserted spectrum analyzer based on Zynq-7000, which uses scheme for FPGA+ARM standalone.☆28Apr 30, 2023Updated 3 years ago
- 雷达信号分选任务是对雷达脉冲序列进行K-means聚类,以判定每个脉冲的所属雷达 1、对 2GHz 以内的信号进行多项滤波,以确定信号的中心频带 2、构建分选数据集,对场景中雷达脉冲序列信号进行仿真,并通过UDP传至开发处理 3、基于C++实现K-means算法并部署…☆21Aug 17, 2023Updated 3 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆42Oct 4, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- FMCW Radar verilog project☆36Jun 15, 2020Updated 6 years ago
- 哈工大软件无线电课设:多相滤波器的原理、实现及其应用,从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果,含答辩PPT、学习笔记和个人总结。☆98Apr 19, 2017Updated 9 years ago
- ☆14Feb 19, 2021Updated 5 years ago
- Design a new OFDM synchronization algorithm, and implement it with both Matlab and Verilog.☆21Feb 8, 2017Updated 9 years ago
- Public repository of the data, scripts and methodology presented in the paper "Towards On-Board SAR Processing with FPGA Accelerators and…☆14Apr 12, 2023Updated 3 years ago
- UART -> AXI Bridge☆78Jul 1, 2021Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆47Jun 22, 2021Updated 5 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆63Jun 23, 2021Updated 5 years ago
- IEEE 802.16 OFDM-based transceiver system☆34Jul 21, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ZYNQ-7000 based data transfer through TCP/IP protocol☆13Apr 20, 2023Updated 3 years ago
- ☆22Apr 4, 2024Updated 2 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆31Dec 17, 2020Updated 5 years ago
- Hardware Acceleration of Banded Smith-Waterman Algorithm on an FPGA using Systolic array based architecture.☆12Nov 26, 2022Updated 3 years ago
- A collection of Opal Kelly provided design resources☆19Updated this week
- TechNexion camera drivers for NVIDIA Jetson.☆12Updated this week
- ☆10Feb 11, 2026Updated 8 months ago
- 使用Cordic算法函数运算,在资源受限的设备上运行(如资源较少的FPGA、嵌入式MCU),避免了浮点运算、乘法、除法,只用移位和加法函数的计算。☆14Mar 22, 2024Updated 2 years ago
- This is use FPGA of Xilinx ZYNQ-7000 ZC702☆17Jul 2, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆24Aug 26, 2017Updated 9 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 6 years ago
- UESTC-雷达信号产生与处理的设计与验证☆19Jun 6, 2019Updated 7 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆32Nov 9, 2015Updated 10 years ago
- IEEE 802.11 OFDM-based transceiver system☆49Dec 15, 2017Updated 8 years ago