RainEggplant / vscode-verilog-integrationLinks
使用 VSCode 舒适地开发 Verilog
☆34Updated 5 years ago
Alternatives and similar repositories for vscode-verilog-integration
Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below
Sorting:
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- ☆65Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆139Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆64Updated last year
- VSCode extension for enhancing verilog☆25Updated last year
- Open IP in Hardware Description Language.☆24Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- ☆68Updated 9 years ago
- AXI协议规范中文翻译版☆159Updated 3 years ago
- ☆64Updated 2 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆122Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆134Updated last year
- Bitmap Processing Library & AXI-Stream Video Image VIP☆33Updated 3 years ago
- 国产VU13P加速卡资料☆76Updated 4 months ago
- ☆86Updated 3 months ago
- A basic SpinalHDL project☆87Updated 4 months ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- OpenXuantie - OpenE902 Core☆153Updated last year
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆72Updated 4 years ago
- ☆36Updated 6 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆138Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆73Updated 3 years ago
- The Ultra-Low Power RISC Core☆15Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆166Updated last month
- A collection of license features from a varity of EDA vendors☆72Updated last year
- Cortex M0 based SoC☆74Updated 3 years ago