Alternatives and similar repositories for vscode-verilog-integration:

Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below

• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆60Updated last year
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆132Updated 9 months ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆114Updated 2 years ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆32Updated last year
• truecrab / VSCode_Extension_Verilog
  VSCode extension for enhancing verilog
  ☆24Updated 11 months ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• OSCPU / ysyxSoC
  ☆80Updated last month
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆71Updated 3 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆57Updated 3 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆19Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆141Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆86Updated 3 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆51Updated 8 months ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆69Updated 3 years ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆36Updated 5 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆30Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆42Updated last week
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆68Updated 3 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆93Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆99Updated 3 years ago
• Reconfigurable-Computing / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆22Updated 2 years ago
• OSCPU / chisel-playground
  ☆63Updated last month
• MichaelMelkor / Vivado_Batch_Mode_Tool
  A tool for those who want to use Vivado's batch mode more easily
  ☆17Updated 5 years ago
• WangXuan95 / Zynq-Tutorial
  使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
  ☆97Updated 6 months ago