RainEggplant / vscode-verilog-integration
使用 VSCode 舒适地开发 Verilog
☆30Updated 4 years ago
Alternatives and similar repositories for vscode-verilog-integration:
Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- ☆63Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆61Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆133Updated 10 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆85Updated 2 months ago
- There is segmentation fault of VCS which should be fixed.☆34Updated last year
- ☆64Updated 2 years ago
- upgrade to e203 (a risc-v core)☆42Updated 4 years ago
- Some useful documents of Synopsys☆70Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- 国产VU13P加速卡资料☆70Updated last month
- SDRAM controller with AXI4 interface☆91Updated 5 years ago
- Verilog极简教程☆36Updated 6 years ago
- ☆64Updated 2 months ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆22Updated 2 years ago
- Implement a bitonic sorting network on FPGA☆42Updated 3 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- A basic SpinalHDL project☆85Updated 2 weeks ago
- a super-simple pipelined verilog divider. flexible to define stages☆55Updated 5 years ago
- Open IP in Hardware Description Language.☆19Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆116Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆58Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- Simple single-port AXI memory interface☆41Updated 10 months ago
- ☆61Updated 9 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Updated 5 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago