RainEggplant / vscode-verilog-integrationLinks
使用 VSCode 舒适地开发 Verilog
☆34Updated 5 years ago
Alternatives and similar repositories for vscode-verilog-integration
Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below
Sorting:
- ☆65Updated 5 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆140Updated last year
- VSCode extension for enhancing verilog☆25Updated last year
- AXI协议规范中文翻译版☆163Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆110Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆123Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- ☆69Updated 9 years ago
- There is segmentation fault of VCS which should be fixed.☆38Updated 2 years ago
- ☆64Updated 3 years ago
- 国产VU13P加速卡资料☆77Updated 6 months ago
- ☆86Updated last week
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Verilog formatter☆198Updated last year
- Some useful documents of Synopsys☆85Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆104Updated last year
- ☆43Updated 3 years ago
- 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆132Updated 3 weeks ago
- AXI Interface Nand Flash Controller (Sync mode)☆96Updated last year
- ☆69Updated 2 weeks ago
- OpenXuantie - OpenE902 Core☆156Updated last year
- The Ultra-Low Power RISC Core☆15Updated 5 years ago
- AXI总线连接器☆103Updated 5 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆163Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆119Updated 12 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated 3 weeks ago