Alternatives and similar repositories for vscode-verilog-integration

Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below

• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆49Updated 2 years ago
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆121Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆72Updated 4 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆152Updated 2 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆24Updated last year
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆129Updated last year
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 5 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆57Updated 11 months ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆36Updated 6 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆36Updated 3 years ago
• BriMonzZY / multi-mode-fft-processor
  R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
  ☆12Updated last month
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆75Updated 3 years ago
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• risclite / verilog-divider
  a super-simple pipelined verilog divider. flexible to define stages
  ☆56Updated 5 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆35Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• truecrab / VSCode_Extension_Verilog
  VSCode extension for enhancing verilog
  ☆24Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago