RainEggplant / vscode-verilog-integrationLinks
使用 VSCode 舒适地开发 Verilog
☆33Updated 4 years ago
Alternatives and similar repositories for vscode-verilog-integration
Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below
Sorting:
- ☆63Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆49Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- AXI协议规范中文翻译版☆153Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- VSCode extension for enhancing verilog☆25Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆121Updated 2 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆137Updated last year
- ☆67Updated 9 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- ☆43Updated 3 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- ☆64Updated 2 years ago
- ☆86Updated 2 months ago
- Verilog formatter☆194Updated last year
- There is segmentation fault of VCS which should be fixed.☆35Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- 《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆130Updated last month
- Open IP in Hardware Description Language.☆24Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆72Updated 4 years ago
- Some useful documents of Synopsys☆76Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- Verilog极简教程☆36Updated 6 years ago
- AHB3-Lite Interconnect☆89Updated last year
- OpenXuantie - OpenE902 Core☆152Updated last year
- AXI总线连接器☆100Updated 5 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆209Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆131Updated last year