RainEggplant / vscode-verilog-integrationLinks
使用 VSCode 舒适地开发 Verilog
☆35Updated 5 years ago
Alternatives and similar repositories for vscode-verilog-integration
Users that are interested in vscode-verilog-integration are comparing it to the libraries listed below
Sorting:
- ☆65Updated 5 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆145Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- VSCode extension for enhancing verilog☆25Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- ☆89Updated 2 months ago
- ☆64Updated 3 years ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- Verilog formatter☆199Updated last year
- 国产VU13P加速卡资料☆79Updated 8 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆108Updated 2 years ago
- ☆72Updated 9 years ago
- Various caches written in Verilog-HDL☆127Updated 10 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆183Updated 2 months ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆144Updated 2 years ago
- RTL Verilog library for various DSP modules☆92Updated 3 years ago
- A basic SpinalHDL project☆86Updated 3 months ago
- There is segmentation fault of VCS which should be fixed.☆38Updated 2 years ago
- 《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆132Updated 3 weeks ago
- AMBA bus generator including AXI, AHB, and APB☆108Updated 4 years ago
- ☆45Updated 3 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- OpenXuantie - OpenE902 Core☆161Updated last year
- AXI Interface Nand Flash Controller (Sync mode)☆97Updated last year
- AXI总线连接器☆105Updated 5 years ago
- ☆66Updated 3 years ago