Alternatives and similar repositories for homebrew-verible

Users that are interested in homebrew-verible are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆129Updated 2 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated last month
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆222Updated last year
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆195Updated last month
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆40Updated 6 years ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• taneroksuz / rv-diios
  6-stage dual-issue in-order superscalar risc-v cpu with floating point unit
  ☆14Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆136Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated last week
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆66Updated last week
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 6 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆77Updated last month
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 6 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆121Updated 4 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 3 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆145Updated 2 weeks ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆49Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago