Alternatives and similar repositories for homebrew-verible:

Users that are interested in homebrew-verible are comparing it to the libraries listed below

• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆98Updated 4 months ago
• imc-trading / svlangserver
  ☆109Updated 10 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated 2 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆157Updated 3 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆91Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆76Updated 3 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated 2 weeks ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆43Updated 3 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆88Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated last week
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆35Updated 8 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆53Updated last month
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆147Updated last month
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆59Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆112Updated 6 months ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆111Updated 6 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆51Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆31Updated 2 weeks ago
• chipsalliance / uvm-verilator
  ☆89Updated last year
• pieter3d / simview
  ☆77Updated last year