VSCode extension for enhancing verilog
☆25Apr 27, 2024Updated 2 years ago
Alternatives and similar repositories for VSCode_Extension_Verilog
Users that are interested in VSCode_Extension_Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Nov 24, 2020Updated 5 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- Hardware Description Language Translator☆17Jun 9, 2026Updated last month
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- nscscc2018☆27Oct 11, 2018Updated 7 years ago
- Verilog formatter☆205Mar 25, 2026Updated 3 months ago
- Contains Matlab codes for Performance analysis of OFDM system over different wireless channel model for variable cyclic prefix length☆17Oct 29, 2020Updated 5 years ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- One Instruction Set Computer☆12Aug 18, 2017Updated 8 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Jun 25, 2026Updated last month
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Swan Benchmark Suite☆13Sep 17, 2025Updated 10 months ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- 开放验证平台NutShell Cache验证案例☆12Dec 2, 2025Updated 7 months ago
- A Visual Studio Code symbols provider based on Ctags☆32Jun 30, 2026Updated 3 weeks ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 3 years ago
- AES RoCC Accelerator☆10May 20, 2021Updated 5 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Note repository for studying Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL).☆15Feb 17, 2025Updated last year
- Comparative analysis of mmWave channel models☆15Dec 1, 2017Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A Verilog (specifically, System Verilog) implementation of the not-yet-finalized SHA-3 winner, Keccak.☆15Apr 8, 2026Updated 3 months ago
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- ☆17Jul 10, 2026Updated 2 weeks ago
- Read only mirror of SVN ChibiOS repository. Official forum http://forum.chibios.org Bugtracker http://sourceforge.net/projects/chibios☆18Sep 2, 2019Updated 6 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- ☆15Jan 11, 2023Updated 3 years ago
- A player using ffmpeg and qt☆11May 17, 2017Updated 9 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 3 years ago
- ☆13Dec 27, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated 3 months ago
- ☆18Feb 25, 2026Updated 5 months ago
- There is segmentation fault of VCS which should be fixed.☆46Sep 19, 2023Updated 2 years ago
- ☆13Aug 8, 2024Updated last year
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 7 years ago
- This is a tool to login qq zone using python, with multithreads to scrapy what you want,such as, message, blogs board, and photos.☆10May 11, 2017Updated 9 years ago
- Translates the DSD/DSF file into WAV file written in C for learning,☆11Feb 21, 2019Updated 7 years ago