Alternatives and similar repositories for VSCode_Extension_Verilog:

Users that are interested in VSCode_Extension_Verilog are comparing it to the libraries listed below

• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• zion-group / VerilogCodingStyle
  ☆60Updated 4 years ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆35Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆58Updated last year
• RainEggplant / vscode-verilog-integration
  使用 VSCode 舒适地开发 Verilog
  ☆29Updated 4 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆57Updated 3 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 6 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆48Updated 6 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆61Updated 3 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆130Updated 8 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆87Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆82Updated 5 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 3 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆58Updated 6 months ago
• MichaelMelkor / Vivado_Batch_Mode_Tool
  A tool for those who want to use Vivado's batch mode more easily
  ☆17Updated 5 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• RicardoNid / ChainsawOld
  ☆23Updated 2 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆68Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆94Updated 4 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆96Updated 3 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆45Updated 4 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆31Updated 4 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆72Updated 3 years ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆30Updated last year
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago