truecrab / VSCode_Extension_VerilogLinks
VSCode extension for enhancing verilog
☆25Updated last year
Alternatives and similar repositories for VSCode_Extension_Verilog
Users that are interested in VSCode_Extension_Verilog are comparing it to the libraries listed below
Sorting:
- ☆65Updated 5 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆103Updated last year
- UVM实战随书源码☆54Updated 6 years ago
- AXI总线连接器☆103Updated 5 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆139Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- Some useful documents of Synopsys☆82Updated 3 years ago
- AXI协议规范中文翻译版☆160Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- AHB3-Lite Interconnect☆90Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆108Updated 2 years ago
- ☆68Updated 9 years ago
- 使用 VSCode 舒适地开发 Verilog☆33Updated 5 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆139Updated last year
- Cortex M0 based SoC☆74Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- AXI DMA 32 / 64 bits☆120Updated 11 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆217Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- ahb scram controller, design and verification☆27Updated 7 years ago
- There is segmentation fault of VCS which should be fixed.☆36Updated last year
- This is the repository for the IEEE version of the book☆71Updated 4 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆119Updated 12 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- round robin arbiter☆75Updated 11 years ago
- automatic-verilog based on vimscript☆269Updated last year
- RTL Verilog library for various DSP modules☆90Updated 3 years ago