alinxalinx / VD100_2023.2View external linksLinks
The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom board.
☆18Jul 9, 2024Updated last year
Alternatives and similar repositories for VD100_2023.2
Users that are interested in VD100_2023.2 are comparing it to the libraries listed below
Sorting:
- This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).☆13Apr 16, 2024Updated last year
- ☆38Jul 6, 2025Updated 7 months ago
- ☆36Aug 19, 2020Updated 5 years ago
- ☆13Jan 28, 2026Updated 2 weeks ago
- ☆10Mar 18, 2020Updated 5 years ago
- W5500底层驱动接口,使用STM32单片机,编写了所有底层操作,并有类socket操作接口,提供所有的测试示例☆10Jan 15, 2019Updated 7 years ago
- Building compiler for generate graph state based on "A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery".☆15Sep 27, 2024Updated last year
- ☆10Jan 10, 2023Updated 3 years ago
- ☆18Updated this week
- my note☆10Jul 19, 2025Updated 6 months ago
- 相当不错的图书,例如《数学之美》、《浪潮之巅》、《TCP/IP卷一/卷二/卷三》等;一些大的上传受限制的文件在这里:https://download.csdn.net/download/singgel☆10Jan 4, 2019Updated 7 years ago
- All Digital Phase-Locked Loop☆12May 22, 2023Updated 2 years ago
- Multi-path UDP protocol - an example implementation☆10Jul 6, 2015Updated 10 years ago
- SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)☆11Jun 19, 2024Updated last year
- An Elixir implementation of the Auto Configuration Server described in the TR-069 specification☆11Jun 1, 2024Updated last year
- Network Tap based on the ZedBoard and Ethernet FMC☆15Nov 21, 2024Updated last year
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Nov 21, 2024Updated last year
- ☆12Aug 29, 2020Updated 5 years ago
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 7 years ago
- Effortlessly Manage and Generate .gitignore files☆11Feb 2, 2026Updated last week
- 考研笔记 (不止数学一)☆17Dec 18, 2024Updated last year
- Testing tools (binary/text) for RS232, QTcpSocket, QLocalSocket☆13Dec 22, 2015Updated 10 years ago
- Asynchronous FIFO for FPGAs☆12Mar 20, 2018Updated 7 years ago
- Tenstorrent Topology (TT-Topology) is a command line utility used to flash multiple NB cards on a system to use specific eth routing conf…☆16Jan 30, 2026Updated 2 weeks ago
- A fast alternative to the standard C/C++ pow() function. With adjustable accuracy-space tradeoff.☆14Jul 12, 2013Updated 12 years ago
- Reverse engineered NanoVNASharp application by Roger Clark with extras XD☆16Aug 23, 2019Updated 6 years ago
- Real Time For the Masses (RTFM), a framework for building concurrent applications, for MSP430 MCUs☆11Jul 29, 2017Updated 8 years ago
- 3-axis Accelerometer☆14Aug 20, 2018Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Xilinx Embedded Software (embeddedsw) Development☆13May 26, 2025Updated 8 months ago
- Source code for LearnQtGuide's Threading and IPC with Qt C++ Course☆15Nov 11, 2019Updated 6 years ago
- APB master and slave developed in RTL.☆21Oct 25, 2025Updated 3 months ago
- WIP☆10Apr 11, 2021Updated 4 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Jun 3, 2016Updated 9 years ago
- ☆14Jan 22, 2026Updated 3 weeks ago
- An AMD/Xilinx Artix 50T FPGA on a Pi5 Hat with PCIe and GPIO interconnects as well as SPI programming☆16Sep 25, 2024Updated last year
- LightWeight IP Application Examples for Xilinx FPGA☆15Jan 19, 2016Updated 10 years ago
- Surface Code Implementation for Qiskit☆11Jul 7, 2020Updated 5 years ago
- Codeplay's tutorial LLDB-MSP430 - as presented at the 2016 EuroLLVM Developers' Meeting in Barcelona.☆11Mar 15, 2016Updated 9 years ago