betrusted-io / gateware
IP submodules, formatted for easier CI integration
☆29Updated last year
Alternatives and similar repositories for gateware:
Users that are interested in gateware are comparing it to the libraries listed below
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆21Updated 6 months ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆28Updated 4 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated 3 weeks ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display☆20Updated 6 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated last year
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated 2 months ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Programmable multichannel ADPCM decoder for FPGA☆23Updated 4 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- ice40 USB Analyzer☆57Updated 4 years ago
- nMigen examples for the ULX3S board☆16Updated 4 years ago
- Apio examples☆34Updated last week
- WCH CH569 SerDes Reverse Engineering☆26Updated 2 years ago
- ☆15Updated last year
- Small footprint and configurable SPI core☆40Updated 3 weeks ago
- Time to Digital Converter (TDC)☆30Updated 4 years ago
- USB 1.1 Device IP Core☆18Updated 7 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Updated 4 years ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆25Updated 5 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆40Updated 9 months ago
- The binaries for SaxonSoc Linux and other configurations☆17Updated last year
- Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more☆12Updated 2 months ago
- iCE40 floorplan viewer☆24Updated 6 years ago