Alternatives and similar repositories for gateware:

Users that are interested in gateware are comparing it to the libraries listed below

• secworks / blake2s
  Verilog implementation of the 32-bit version of the Blake2 hash function
  ☆21Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆55Updated 3 weeks ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• hydrausb3 / wch-ch569-serdes
  WCH CH569 SerDes Reverse Engineering
  ☆26Updated 2 years ago
• antmicro / ecp5-dc-scm
  Experimental Lattice ECP5-driven Data Center Security Communication Module
  ☆21Updated 7 months ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆28Updated 4 years ago
• gatecat / meowality
  ☆15Updated last year
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 3 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆17Updated last year
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆28Updated 2 years ago
• j-marjanovic / ocs-tray-mezzanine-adapter
  PCIe adapter for an FPGA accelerator for Open CloudServer
  ☆22Updated 4 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆36Updated last year
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated 2 months ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated last week
• enjoy-digital / litex_rp2040_pmod_test
  Test of a RP2040 PMOD attached to a LiteX SoC.
  ☆25Updated last year
• smunaut / iua
  ice40 USB Analyzer
  ☆58Updated 4 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆39Updated last year
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 6 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆53Updated 2 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆56Updated 3 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago