betrusted-io / gatewareLinks
IP submodules, formatted for easier CI integration
☆30Updated last month
Alternatives and similar repositories for gateware
Users that are interested in gateware are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆65Updated last week
- understanding the tinyfpga bootloader☆24Updated 7 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- Small footprint and configurable SPI core☆45Updated last week
- Test of the USB3 IP Core from Daisho on a Xilinx device☆99Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Low-cost ECP5 FPGA development board☆80Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- PicoRV☆43Updated 5 years ago
- Betrusted embedded controller (UP5K)☆48Updated last year
- Siglent SDS1x0xX-E FPGA bitstreams☆42Updated 10 months ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆90Updated 11 months ago
- ice40 USB Analyzer☆57Updated 5 years ago
- ☆44Updated 7 months ago
- VexRiscv-SMP integration test with LiteX.☆26Updated 4 years ago
- ☆63Updated 5 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated 6 months ago
- ECPDAP allows you to program ECP5 FPGAs and attached SPI flash using CMSIS-DAP probes in JTAG mode.☆67Updated 2 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆30Updated 5 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago
- PCIe analyzer experiments☆62Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated last month
- Utilities for the ECP5 FPGA☆17Updated 4 years ago
- 妖刀夢渡☆63Updated 6 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- Simplified environment for litex☆14Updated 5 years ago
- Time to Digital Converter (TDC)☆35Updated 4 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆39Updated last year