Alternatives and similar repositories for WaveView:

Users that are interested in WaveView are comparing it to the libraries listed below

• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 3 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆23Updated 2 months ago
• socrocket / core
  SoCRocket - Core Repository
  ☆34Updated 7 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆21Updated last month
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆82Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆56Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆94Updated 5 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆35Updated 2 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 3 months ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• merledu / TileLink
  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
  ☆20Updated 4 years ago
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆31Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆18Updated 10 months ago
• antmicro / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆20Updated this week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 8 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆47Updated 2 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆18Updated last month
• aolofsson / POSH
  ☆40Updated 5 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆50Updated last year
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆12Updated 7 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆15Updated 5 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 7 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago