jialinlu / SDM-DSELinks
☆11Updated last year
Alternatives and similar repositories for SDM-DSE
Users that are interested in SDM-DSE are comparing it to the libraries listed below
Sorting:
- ☆27Updated last year
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆47Updated 5 years ago
- The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design☆63Updated 5 months ago
- ☆306Updated 2 weeks ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Updated 9 months ago
- Machine Generated Analog IC Layout☆239Updated last year
- A seamless python to Cadence Virtuoso Skill interface☆220Updated 4 months ago
- Read Spectre PSF files☆64Updated last month
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆151Updated last month
- ☆50Updated last month
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆93Updated 2 months ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆205Updated last month
- BAG2 workspace for fake PDK (cds_ff_mpt)☆58Updated 5 years ago
- LAYout with Gridded Objects v2☆57Updated 3 weeks ago
- ☆149Updated 2 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆10Updated 3 years ago
- awesome-Analog-IC-Design-Automation☆39Updated 2 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆69Updated 2 years ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated 10 months ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆45Updated last month
- my cadence/virtuoso/icfb skill functions develloped over the years☆134Updated 3 months ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆169Updated 8 months ago
- Gm over Id methodology☆24Updated 3 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆14Updated last year
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆32Updated last year
- ☆65Updated 3 months ago
- BAG framework☆30Updated 6 months ago
- An EDA tool for automatic device sizing using Gm/Id method.☆14Updated 10 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago