jialinlu / SDM-DSELinks
☆11Updated last year
Alternatives and similar repositories for SDM-DSE
Users that are interested in SDM-DSE are comparing it to the libraries listed below
Sorting:
- ☆27Updated last year
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆146Updated 3 weeks ago
- awesome-Analog-IC-Design-Automation☆37Updated 2 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆47Updated 5 years ago
- ☆48Updated 3 weeks ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆12Updated 8 months ago
- The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design☆59Updated 5 months ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆57Updated 5 years ago
- Read Spectre PSF files☆64Updated 3 weeks ago
- Gm over Id methodology☆24Updated 3 years ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆90Updated 2 months ago
- ☆149Updated 2 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆68Updated 2 years ago
- ☆303Updated 3 months ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated 10 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 7 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆14Updated last year
- LAYout with Gridded Objects v2☆57Updated this week
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆167Updated 7 months ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆23Updated 9 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆42Updated 7 months ago
- Solve one design problem each day for a month☆43Updated 2 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆30Updated last year
- Machine Generated Analog IC Layout☆238Updated last year
- An EDA tool for automatic device sizing using Gm/Id method.☆14Updated 9 months ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆33Updated 3 years ago
- A python3 gm/ID starter kit☆49Updated 9 months ago
- ☆62Updated 3 months ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆14Updated last year