jialinlu / SDM-DSE
☆11Updated last year
Alternatives and similar repositories for SDM-DSE:
Users that are interested in SDM-DSE are comparing it to the libraries listed below
- ☆27Updated last year
- ☆146Updated 2 years ago
- Machine Generated Analog IC Layout☆218Updated 8 months ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆54Updated 4 years ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆11Updated 3 months ago
- ☆277Updated last month
- LAYout with Gridded Objects v2☆55Updated 3 months ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆61Updated 9 months ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆41Updated 4 years ago
- Read Spectre PSF files☆55Updated 2 months ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆114Updated 10 months ago
- SKY130 SRAM macros generated by SRAM 22☆11Updated last month
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆39Updated this week
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆68Updated 2 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆13Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆61Updated last year
- Artificial Netlist Generator☆35Updated 10 months ago
- Analog Placement Quality Prediction☆20Updated last year
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆11Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆141Updated 2 months ago
- awesome-Analog-IC-Design-Automation☆30Updated last year
- ☆36Updated 9 months ago
- ☆28Updated 3 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆33Updated 6 months ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆23Updated 5 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆52Updated 7 years ago
- BAG framework☆22Updated 3 weeks ago
- Circuit release of the MAGICAL project☆30Updated 5 years ago
- ADC Performance Survey 1997-2024 (ISSCC & VLSI Circuit Symposium)☆175Updated 5 months ago
- ☆18Updated 6 months ago