A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)
☆12Jan 8, 2021Updated 5 years ago
Alternatives and similar repositories for verilog-LDPC-decoder
Users that are interested in verilog-LDPC-decoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is my MTech Thesis Dissertation Topic.☆11Oct 21, 2022Updated 4 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆54Sep 17, 2017Updated 9 years ago
- Low Density Parity Check Decoder☆19Sep 12, 2016Updated 10 years ago
- NMS_decode☆14Jul 17, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter☆14Mar 21, 2017Updated 9 years ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- FPGA based image processing pipeline using zedboard, able to accelerate openCV functions☆17Apr 29, 2020Updated 6 years ago
- ☆13Aug 24, 2026Updated 2 months ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- Yet another port of FreeRTOS to Beaglebone Black (AM335x)☆11Dec 8, 2016Updated 9 years ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 4 years ago
- Core protocol to AXI bridge☆11Sep 30, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DVB-S2 LDPC Decoder☆32Jul 17, 2014Updated 12 years ago
- A project demonstrate how to config ad9361 to TX mode☆13Dec 9, 2018Updated 7 years ago
- Wi-Fi LDPC codec Verilog IP core☆21Jun 30, 2026Updated 4 months ago
- ☆16Sep 17, 2026Updated last month
- Simple Simulator of ARMv6m instructions☆18May 23, 2017Updated 9 years ago
- Building a simple oscilloscope using FPGA board and PCB.☆22Dec 30, 2020Updated 5 years ago
- NVMe driver for MicroBlaze on Zynq UltraScale+ MPSoC☆11Feb 7, 2020Updated 6 years ago
- This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by …☆11May 11, 2023Updated 3 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Implementation of a circular queue in hardware using verilog.☆18Mar 22, 2019Updated 7 years ago
- Notes from learning RISC-V☆12Jun 30, 2026Updated 4 months ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 3 years ago
- This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologi…☆12Oct 19, 2024Updated 2 years ago
- Hardware implementation (Verilog) and Software Implementation (MATLAB) of IEEE's 802.11a standard for transmitter and receiver sides of W…☆14Feb 19, 2022Updated 4 years ago
- ☆14Oct 22, 2026Updated last week
- A fork of TinyMLPerf modified to use our of TensorFlow Lite for Microcontrollers utilises a part of the RISC-V Vector Extension to improv…☆11Jan 18, 2021Updated 5 years ago
- This project implements a Hamming encoder and decoder using Verilog to correct single-bit errors in data transmission. It includes Verilo…☆11Aug 2, 2024Updated 2 years ago
- FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.☆20Apr 26, 2017Updated 9 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Model Context Protocol (MCP) server for OpenROAD☆31Oct 24, 2026Updated last week
- Turbo coder and decoder☆12Oct 11, 2023Updated 3 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 10 months ago
- C Crypto library supporting DES, AES128, SHA256, CCM-AES128, ECDSA, ECDH, PKCS#1 v1.5☆15Jan 24, 2022Updated 4 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆22Apr 15, 2018Updated 8 years ago
- STM32 target playground for spiffs☆18Aug 11, 2016Updated 10 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆135Oct 5, 2026Updated 3 weeks ago