bol-edu / caravel-soc_fpga-lab
☆15Updated last month
Alternatives and similar repositories for caravel-soc_fpga-lab:
Users that are interested in caravel-soc_fpga-lab are comparing it to the libraries listed below
- AXI Interconnect☆47Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- ☆29Updated 5 years ago
- AXI总线连接器☆94Updated 4 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆57Updated last year
- Architectural design of data router in verilog☆28Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆49Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆54Updated 2 years ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆80Updated 5 years ago
- IEEE Executive project for the year 2021-2022☆8Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- Some useful documents of Synopsys☆62Updated 3 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- UVM and System Verilog Manuals☆39Updated 6 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- ☆39Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago