Alternatives and similar repositories for caravel-soc_fpga-lab

Users that are interested in caravel-soc_fpga-lab are comparing it to the libraries listed below

• bol-edu / caravel-soc

  View on GitHub
  ☆30Jul 9, 2023Updated 2 years ago
• dpretet / friscv

  View on GitHub
  RISCV CPU implementation in SystemVerilog
  ☆32Oct 1, 2025Updated 4 months ago
• karthik-r-rao / VLSI_Physical_Design_Tool

  View on GitHub
  A simple tool to demonstrate the physical design steps of VLSI Design Flow.
  ☆10Dec 13, 2020Updated 5 years ago
• HackerFoo / nitefury-popr

  View on GitHub
  ☆10Mar 18, 2020Updated 5 years ago
• siyueyinghua / UVMInPracticesByZhangQiang

  View on GitHub
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆42Mar 7, 2021Updated 4 years ago
• rfdonnelly / docker-questa

  View on GitHub
  A Docker image for Mentor/Siemens Questa
  ☆13Sep 26, 2023Updated 2 years ago
• vcdlk / An-oscilloscope-based-on-stm32H743

  View on GitHub
  An oscilloscope based on stm32H743
  ☆10Jan 3, 2020Updated 6 years ago
• EECS150 / fpga_labs_fa21

  View on GitHub
  FPGA Labs for EECS 151/251A (Fall 2021)
  ☆11Oct 20, 2021Updated 4 years ago
• w4mhi / digipi

  View on GitHub
  Files for the DigiPi project made by Craig Lamparter
  ☆11Jul 22, 2025Updated 6 months ago
• Joshuaalbert / IonoTomo

  View on GitHub
  Ionospheric tomography for radio astronomy using ray tracing, and radio observation simulation
  ☆10Jul 15, 2018Updated 7 years ago
• bol-edu / soclab-nthusp23

  View on GitHub
  ☆15Sep 24, 2023Updated 2 years ago
• antmicro / usb-test-suite-cocotb-usb

  View on GitHub
  ☆10Apr 8, 2021Updated 4 years ago
• antmicro / simple-chisel-axi-peripheral

  View on GitHub
  ☆12May 8, 2025Updated 9 months ago
• xfguo / spi

  View on GitHub
  SPI Master Core clone from OpenCores
  ☆12Oct 4, 2013Updated 12 years ago
• verilog-meetup / systemverilog-microarchitecture-challenge-for-ai-2

  View on GitHub
  SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.
  ☆22Sep 4, 2025Updated 5 months ago
• efabless / EF_UART

  View on GitHub
  Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
  ☆15Feb 18, 2025Updated 11 months ago
• santhiyaskumar / FPGA_Codec2Encoder

  View on GitHub
  Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.
  ☆13Mar 29, 2020Updated 5 years ago
• FPGA-MAFIA / fpga_mafia

  View on GitHub
  Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
  ☆17Feb 2, 2026Updated 2 weeks ago
• qmj0923 / 2020-Fall-NJU-Experiments-in-Digital-Logical-Circuits

  View on GitHub
  2020秋-南大数电实验
  ☆10Jan 24, 2021Updated 5 years ago
• antmicro / ahb-tl-bridge

  View on GitHub
  SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge
  ☆13Sep 9, 2022Updated 3 years ago
• renatosoriano / Hands-On-RTOS-with-Microcontrollers-Book-Projects

  View on GitHub
  Projects, Codes, Notes, Fixes and Results for book "Hands-On RTOS with Microcontrollers" by Brian Amos and published by Packt.
  ☆11Mar 15, 2025Updated 11 months ago
• msyksphinz-self / chisel-soc

  View on GitHub
  ☆10Dec 28, 2020Updated 5 years ago
• zxc31070109 / ICLAB2022FALL

  View on GitHub
  國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授
  ☆14Mar 3, 2023Updated 2 years ago
• kdg-auts / ALINX-AX309

  View on GitHub
  Laboratory workshop for ALINX AX309 development board (with FPGA Spartan 6)
  ☆15Mar 23, 2025Updated 10 months ago
• jgillis / madnlp_demo

  View on GitHub
  ☆12Aug 1, 2024Updated last year
• freecores / dma_axi

  View on GitHub
  AXI DMA 32 / 64 bits
  ☆124Jul 17, 2014Updated 11 years ago
• synergy-noc-generators / Proteus

  View on GitHub
  ☆10Jan 25, 2023Updated 3 years ago
• ZipCPU / wbspi

  View on GitHub
  A collection of SPI related cores
  ☆21Nov 12, 2024Updated last year
• ncsg-group / csRNA

  View on GitHub
  ☆13May 30, 2024Updated last year
• sw-song / RealTime_Gesture_VolumeControl

  View on GitHub
  Computer Vision, Pose Estimation, Python
  ☆12May 21, 2021Updated 4 years ago
• emwzq / example_uvm

  View on GitHub
  UVM实战随书源码
  ☆58Jan 22, 2019Updated 7 years ago
• pezy-computing / flgen

  View on GitHub
  Filelist generator
  ☆20Feb 3, 2026Updated 2 weeks ago
• Jasonyanyusong / ysyx-npc-workbench

  View on GitHub
  一生一芯RISCV处理器核代码仓库（包括相关工具）
  ☆15Sep 11, 2024Updated last year
• kkudrolli / USB-Host

  View on GitHub
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆15Jan 13, 2015Updated 11 years ago
• dan-rodrigues / mobile-fpga-bluetooth-demo

  View on GitHub
  Simple BLE demo using an iOS app (SwiftUI), an ESP32 (Python) and an FPGA (Verilog)
  ☆16Dec 12, 2020Updated 5 years ago
• kaitoukito / YSYX-NJU-Group

  View on GitHub
  YSYX RISC-V Project NJU Study Group
  ☆16Jan 3, 2025Updated last year
• FDUCSLG / Arch-2022Spring-FDU

  View on GitHub
  ☆10Jun 7, 2022Updated 3 years ago
• eisl-nctu / falco

  View on GitHub
  A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
  ☆15Jan 14, 2022Updated 4 years ago
• kazuar / raspberrypi_voice_control

  View on GitHub
  ☆13Aug 15, 2015Updated 10 years ago