bol-edu / caravel-soc_fpga-lab
☆17Updated last month
Alternatives and similar repositories for caravel-soc_fpga-lab:
Users that are interested in caravel-soc_fpga-lab are comparing it to the libraries listed below
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- AXI Interconnect☆47Updated 3 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 8 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- ☆32Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆145Updated last week
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- Some useful documents of Synopsys☆72Updated 3 years ago
- AXI DMA 32 / 64 bits☆112Updated 10 years ago
- Two Level Cache Controller implementation in Verilog HDL☆43Updated 4 years ago
- ☆43Updated 3 years ago
- ☆51Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- AXI总线连接器☆97Updated 5 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆18Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- ☆19Updated 2 years ago
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago