☆21Apr 8, 2025Updated last year
Alternatives and similar repositories for caravel-soc_fpga-lab
Users that are interested in caravel-soc_fpga-lab are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆57Sep 5, 2023Updated 2 years ago
- ☆30Jul 9, 2023Updated 2 years ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- RISCV CPU implementation in SystemVerilog☆32Mar 17, 2026Updated last month
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆25Sep 4, 2025Updated 8 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains ever…☆37Jul 29, 2024Updated last year
- ☆13May 8, 2025Updated last year
- ☆10Jan 25, 2023Updated 3 years ago
- ☆13May 30, 2024Updated last year
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- Some design examples of Verilog about digital circuits☆30Nov 21, 2020Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Nov 19, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆10Apr 8, 2021Updated 5 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆19Jul 17, 2019Updated 6 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- Design real-time image processing, object recognition and PID control for Autonomous Drone.☆35Nov 26, 2017Updated 8 years ago
- OpenTitan: Open source silicon root of trust☆10Feb 5, 2020Updated 6 years ago
- HLS code for Network on Chip (NoC)☆23Sep 11, 2020Updated 5 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆29Jul 31, 2019Updated 6 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆32Jun 27, 2022Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆19May 1, 2023Updated 3 years ago
- Zynq-7000 DPU TRD☆49Jul 19, 2019Updated 6 years ago
- Simulation of Multi-Path-RDMA algorithm based on ns-3☆21May 12, 2024Updated last year
- ☆43Apr 6, 2023Updated 3 years ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆42Mar 7, 2021Updated 5 years ago
- FAST-9 Accelerator for Corner Detection☆38Jan 1, 2021Updated 5 years ago
- Emulating Quantum Circuits on FPGAs☆29Nov 22, 2023Updated 2 years ago
- 2020秋-南大数电实验☆10Jan 24, 2021Updated 5 years ago
- ☆26Feb 20, 2024Updated 2 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Nova-based SHA256 benchmarks☆31Jun 7, 2025Updated 11 months ago
- AXI DMA 32 / 64 bits☆127Jul 17, 2014Updated 11 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- FPGA Labs for EECS 151/251A (Fall 2021)☆12Oct 20, 2021Updated 4 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated 2 months ago
- 🧠 Unlock your mind with Memory Palace: Explore AI-guided Memory Palaces to master the Loci method, generate vivid imagery, and enhance r…☆42Apr 30, 2026Updated last week
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago