Shra1-25 / Deep-Learning-implementaion-on-FPGA-using-MATLAB
This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code generator cannot generate codes from Neural Network toolbox of MATLAB, I have written this MATLAB scripts using simple MATLAB functions that can be used for HDL code generation using HDL coder.
☆11Updated 5 years ago
Alternatives and similar repositories for Deep-Learning-implementaion-on-FPGA-using-MATLAB
Users that are interested in Deep-Learning-implementaion-on-FPGA-using-MATLAB are comparing it to the libraries listed below
Sorting:
- An AXI DDR3 SDRAM controller for FPGA☆36Updated last year
- Interface Protocol in Verilog☆49Updated 5 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆18Updated last year
- ☆19Updated 2 years ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆43Updated 6 years ago
- AHB Bus lite v3.0☆15Updated 5 years ago
- FPGA 同步FIFO与异步FIFO☆30Updated 6 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- These scrpits will be extremly useful in parsing Verilog files☆7Updated 10 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆11Updated 10 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆53Updated 3 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆42Updated 8 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆16Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 9 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆10Updated 7 years ago
- 基于FPGA的FFT☆16Updated 6 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 4 years ago
- fpga跑sobel识别算法☆35Updated 4 years ago
- FPGA implementation of a handwritten digit recognition system based on k-nearest-neighbors (k-NN) classifier algorithm.☆21Updated 7 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆15Updated 4 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆16Updated 6 years ago