Shra1-25 / Deep-Learning-implementaion-on-FPGA-using-MATLABLinks
This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code generator cannot generate codes from Neural Network toolbox of MATLAB, I have written this MATLAB scripts using simple MATLAB functions that can be used for HDL code generation using HDL coder.
☆13Updated 5 years ago
Alternatives and similar repositories for Deep-Learning-implementaion-on-FPGA-using-MATLAB
Users that are interested in Deep-Learning-implementaion-on-FPGA-using-MATLAB are comparing it to the libraries listed below
Sorting:
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Updated 4 years ago
- AHB Bus lite v3.0☆16Updated 6 years ago
- ☆28Updated 6 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Updated 2 years ago
- ☆19Updated 3 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆11Updated 7 years ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆15Updated last month
- ABP Accelerated VIP☆22Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Updated last year
- An AXI DDR3 SDRAM controller for FPGA☆43Updated 2 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆32Updated 4 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆26Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- A 32 point radix-2 FFT module written in Verilog☆24Updated 5 years ago
- ☆13Updated 6 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Updated 7 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated this week
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 months ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated last month
- Projects and Labs for the Parallel Programming for FPGAs book☆20Updated last month
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆27Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- ☆20Updated 3 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆11Updated 2 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆17Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago