Shra1-25 / Deep-Learning-implementaion-on-FPGA-using-MATLABLinks
This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code generator cannot generate codes from Neural Network toolbox of MATLAB, I have written this MATLAB scripts using simple MATLAB functions that can be used for HDL code generation using HDL coder.
☆13Updated 5 years ago
Alternatives and similar repositories for Deep-Learning-implementaion-on-FPGA-using-MATLAB
Users that are interested in Deep-Learning-implementaion-on-FPGA-using-MATLAB are comparing it to the libraries listed below
Sorting:
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Updated 4 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆12Updated 7 years ago
- ☆28Updated 6 months ago
- AHB Bus lite v3.0☆17Updated 6 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago
- ☆19Updated 3 years ago
- An AXI DDR3 SDRAM controller for FPGA☆44Updated 2 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Updated 7 years ago
- ABP Accelerated VIP☆22Updated 3 years ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆15Updated 2 months ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆26Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆63Updated 3 years ago
- ☆34Updated 6 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 months ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Updated last year
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆33Updated 4 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Updated 5 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆28Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Updated 2 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆11Updated 2 years ago
- minimal code to access ps DDR from PL☆22Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆39Updated 8 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆13Updated 2 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Updated 6 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated 3 weeks ago
- Low Density Parity Check Decoder☆18Updated 9 years ago