High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
☆45Jul 25, 2024Updated 2 years ago
Alternatives and similar repositories for HLS-CNN
Users that are interested in HLS-CNN are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Convolutional Neural Network Using High Level Synthesis☆88Sep 23, 2020Updated 6 years ago
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆18Aug 22, 2026Updated last month
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Oct 3, 2023Updated 2 years ago
- HLS_YOLOV3☆25Jan 11, 2024Updated 2 years ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆19Sep 15, 2020Updated 6 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆12Sep 30, 2020Updated 5 years ago
- CNN simd based accelerator using Vitis HLS☆12Jul 15, 2022Updated 4 years ago
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆30Oct 6, 2021Updated 4 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆86May 30, 2021Updated 5 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 4 years ago
- ☆15Aug 10, 2023Updated 3 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆30Jul 31, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An inhouse RISC-V 32-bits CPU☆22Updated this week
- A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.☆12Jul 29, 2021Updated 5 years ago
- LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framew…☆33Jul 6, 2026Updated 2 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated 2 years ago
- ☆27Mar 19, 2021Updated 5 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆16Feb 17, 2019Updated 7 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆29Oct 31, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 银行基本业务系统后端实现☆10Nov 9, 2018Updated 7 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆20Apr 17, 2016Updated 10 years ago
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆10Jun 25, 2022Updated 4 years ago
- ☆18Feb 22, 2018Updated 8 years ago
- Drastically Reducing the Number of Trainable Parameters in Deep CNNs by Inter-layer Kernel-sharing☆14Mar 28, 2023Updated 3 years ago
- FPGA Clock Configuration Device Driver for Linux☆34Dec 4, 2025Updated 9 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- use Zybo z7-20☆17May 21, 2025Updated last year
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆26Dec 29, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hardware and Software Co-design implementations☆16Dec 5, 2019Updated 6 years ago
- 可运行☆40Jul 1, 2022Updated 4 years ago
- A course based on FINN with hands on Lectures, Examples and Labs to go from 0 to a full custom Quantized Neural Network running on your v…☆48Jul 3, 2025Updated last year
- PCMCsim: An Accurate Phase-Change Memory Controller Simulator and its Performance Analysis (ISPASS 2022)☆10Aug 3, 2024Updated 2 years ago
- ☆15Oct 5, 2023Updated 2 years ago
- ☆31Mar 22, 2026Updated 6 months ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago