StefanSredojevic / Deep-Neural-Network-Hardware-AcceleratorView external linksLinks
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
☆112Apr 3, 2020Updated 5 years ago
Alternatives and similar repositories for Deep-Neural-Network-Hardware-Accelerator
Users that are interested in Deep-Neural-Network-Hardware-Accelerator are comparing it to the libraries listed below
Sorting:
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆105Dec 14, 2023Updated 2 years ago
- Verilog Generator of Neural Net Digit Detector for FPGA☆314Sep 7, 2022Updated 3 years ago
- FPGA Accelerator for CNN using Vivado HLS☆331Oct 25, 2021Updated 4 years ago
- ☆14Mar 13, 2023Updated 2 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆142Mar 30, 2018Updated 7 years ago
- APB Logic☆23Jan 22, 2026Updated 3 weeks ago
- DynamicVINO is an open-source C++ library for establishing easy-to-use, extensible and scalable deep learning inference system for Intel…☆14Aug 21, 2018Updated 7 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆197Dec 15, 2017Updated 8 years ago
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 8 years ago
- ☆17Jul 21, 2017Updated 8 years ago
- ☆24May 26, 2022Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Dec 14, 2019Updated 6 years ago
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆785Dec 10, 2019Updated 6 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆233Dec 18, 2018Updated 7 years ago
- Fully Hardware-Based Stochastic Neural Network☆22Jan 23, 2025Updated last year
- ☆26Dec 12, 2022Updated 3 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆219Aug 4, 2019Updated 6 years ago
- ☆91Apr 15, 2020Updated 5 years ago
- A pipelined brainfuck softcore in Verilog☆19Aug 5, 2014Updated 11 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Sep 23, 2020Updated 5 years ago
- Updated version of the XUP Workshops☆12Aug 10, 2018Updated 7 years ago
- Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.☆11May 10, 2018Updated 7 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks☆623Jan 3, 2020Updated 6 years ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆769May 26, 2017Updated 8 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆187Jan 28, 2017Updated 9 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- betrusted.io main SoC design☆14Jan 30, 2020Updated 6 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆57Jan 21, 2017Updated 9 years ago
- Python on Zynq FPGA for Convolutional Neural Networks☆624May 15, 2018Updated 7 years ago
- Custom Coprocessor Interface for VexRiscv☆10Sep 19, 2018Updated 7 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Board files for building PYNQ linux for Zybo☆14Mar 30, 2019Updated 6 years ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Dec 6, 2023Updated 2 years ago
- An AIoT project based on PYNQ-Z2 FPGA Evaluation board. Reading image from usb camera and running yolov3-tiny detection with DPU and usin…☆11May 12, 2022Updated 3 years ago