Alternatives and similar repositories for PySpice-Library:

Users that are interested in PySpice-Library are comparing it to the libraries listed below

• martinjankoehler / klayout-pex
  Parasitic Extraction for KLayout
  ☆20Updated last week
• ediloren / EM-Workbench-for-FreeCAD
  This project is dedicated to building an ElectroMagnetic workbench for FreeCAD. FreeCAD is a free 3D parametric CAD. FreeCAD is used as p…
  ☆62Updated last year
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆23Updated 4 years ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated last week
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆29Updated last month
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago
• capn-freako / PyAMI
  Python package for IBIS-AMI model development and testing
  ☆28Updated last week
• MatBucher / ekv3model
  ☆17Updated last year
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆37Updated last year
• Qucs / ADMS
  ADMS is a code generator for the Verilog-AMS language
  ☆99Updated 2 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆52Updated 2 years ago
• KenKundert / rlc_chart
  A library that renders impedance charts that include capacitance and inductance grids.
  ☆13Updated last month
• drom / logidrom
  Digital Circuit rendering engine
  ☆38Updated last year
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 3 years ago
• psychogenic / microcotb
  micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
  ☆13Updated 2 months ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆76Updated 4 months ago
• PyLCARS / PySpiceExsamples
  Collection of exsample showing the usage of PySpice and how to move beyond the limts of SPICE with python
  ☆28Updated 6 years ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆34Updated 5 years ago
• henjo / pyoa
  Donald Amundson's Python interface to OpenAccess IC design data API
  ☆16Updated 15 years ago
• zwh42 / KLayout-PyMacros
  Python library for KLayout (https://www.klayout.de/)
  ☆24Updated 5 years ago
• mbalestrini / tinytapeout_gds_viewer
  ☆13Updated last month
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• hugodiasg / asitic-example
  ☆11Updated 6 months ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆23Updated last year
• mabrains / caravel_analog_rf
  Analog and RF blocks on Skywaters 130nm
  ☆11Updated 2 years ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆43Updated 2 weeks ago
• mabrains / sky130_klayout_pdk
  Skywater 130nm Klayout Device Generators PDK
  ☆31Updated 9 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆36Updated 4 months ago