Alternatives and similar repositories for vmanager-plugin:

Users that are interested in vmanager-plugin are comparing it to the libraries listed below

• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆25Updated last week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆29Updated this week
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated 3 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆36Updated 8 years ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 5 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 3 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 7 months ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆33Updated 9 years ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• mtdsousa / antlr4-verilog-python
  Generated files from ANTLR4 for Verilog parsing in Python
  ☆12Updated 2 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated last year
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆57Updated 6 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆26Updated 8 months ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 3 years ago
• merldsu / PY_UVM_Framework
  This repo contain the PY-UVM Framework for different RISC-V Cores
  ☆31Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆25Updated last week
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆23Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆48Updated 2 weeks ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆49Updated last year
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 3 years ago
• Minres / RDL-Editor
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Updated 11 months ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 3 months ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 8 months ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆34Updated 7 months ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆53Updated 4 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆60Updated 3 months ago