fontamsoc / pu32
☆15Updated last year
Alternatives and similar repositories for pu32:
Users that are interested in pu32 are comparing it to the libraries listed below
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆41Updated last month
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Basic Pong you can extend with rotary, sound, vga generator and autopilot☆11Updated 3 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆70Updated 9 months ago
- A SoC for DOOM☆17Updated 4 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- USB virtual model in C++ for Verilog☆29Updated 6 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated last month
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Virtual development board for HDL design☆41Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- Template Verilator project for beginners☆12Updated 2 years ago
- A collection of SPI related cores☆16Updated 5 months ago
- A padring generator for ASICs☆25Updated last year
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆12Updated last month
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 11 months ago
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago
- ☆15Updated 5 months ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆17Updated last year
- a small simple slow serial FPGA core☆16Updated 4 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆18Updated 2 weeks ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago