MartaAndronic / NeuraLUT
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
☆15Updated 9 months ago
Alternatives and similar repositories for NeuraLUT:
Users that are interested in NeuraLUT are comparing it to the libraries listed below
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆45Updated 11 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆13Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆47Updated this week
- ☆71Updated last year
- ☆22Updated 2 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆38Updated 4 months ago
- An HLS based winograd systolic CNN accelerator☆49Updated 3 years ago
- ☆18Updated 2 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆28Updated 2 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆28Updated 2 months ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆56Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Library of approximate arithmetic circuits☆53Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆28Updated 6 months ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- ☆33Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆34Updated 2 years ago