awai54st / Enabling-Binary-Neural-Network-Training-on-the-EdgeLinks
☆19Updated 3 years ago
Alternatives and similar repositories for Enabling-Binary-Neural-Network-Training-on-the-Edge
Users that are interested in Enabling-Binary-Neural-Network-Training-on-the-Edge are comparing it to the libraries listed below
Sorting:
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆26Updated last year
- ☆35Updated 6 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆93Updated 4 years ago
- CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices☆47Updated 5 years ago
- ☆59Updated 5 years ago
- Approximate layers - TensorFlow extension☆26Updated 5 months ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- ☆71Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆23Updated 3 years ago
- ☆30Updated 6 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated last week
- ☆72Updated 2 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- ☆41Updated last year
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- ☆35Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- ☆37Updated 6 months ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆52Updated last year
- FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.☆26Updated 2 years ago
- NeuraLUT-Assemble☆40Updated last month
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆88Updated 2 months ago
- GoldenEye is a functional simulator with fault injection capabilities for common and emerging numerical formats, implemented for the PyTo…☆26Updated 11 months ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆16Updated 2 years ago
- ☆18Updated 2 years ago
- ☆25Updated 2 years ago