dominic-meads / HDMI_FPGA

Related projects: ⓘ

• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆28Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆34Updated 3 months ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆69Updated 5 months ago
• freecores / uart16550
  UART 16550 core
  ☆29Updated 10 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆74Updated 4 years ago
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆25Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆72Updated last year
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆34Updated 7 years ago
• fredrequin / verilator_gowin
  Re-coded Gowin GW1N primitives for Verilator use
  ☆13Updated 2 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆16Updated 10 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆57Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆58Updated last year
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆22Updated last year
• geraked / verilog-rle
  Verilog Implementation of Run Length Encoding for RGB Image Compression
  ☆23Updated 3 years ago
• gtjennings1 / JPEG_Encoder
  ☆15Updated 6 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆47Updated last month
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆49Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆84Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆75Updated 5 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆45Updated 8 years ago
• taneroksuz / fpu
  IEEE 754 floating point library in system-verilog and vhdl
  ☆53Updated 3 months ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆12Updated 9 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆23Updated 9 years ago
• barbedo / verilog-book
  Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
  ☆19Updated 6 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆40Updated 9 months ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆15Updated 10 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆44Updated 4 years ago