bieganski / mtkcpuLinks
RISC-V CPU implementation in Amaranth HDL (aka nMigen)
☆33Updated last year
Alternatives and similar repositories for mtkcpu
Users that are interested in mtkcpu are comparing it to the libraries listed below
Sorting:
- Another size-optimized RISC-V CPU for your consideration.☆59Updated last week
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- System on Chip toolkit for Amaranth HDL☆98Updated last week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Updated 2 months ago
- A Risc-V SoC for Tiny Tapeout☆47Updated 2 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- The Critical Path - a rambly FPGA blog☆51Updated 5 years ago
- FPGA Odysseus with ULX3S☆69Updated 2 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆92Updated 7 months ago
- Miscellaneous ULX3S examples (advanced)☆82Updated 7 months ago
- Graded exercises for nMigen (WIP)☆55Updated 5 years ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 4 years ago
- ☆44Updated 10 months ago
- Board definitions for Amaranth HDL☆122Updated 5 months ago
- DDR3 controller for nMigen (WIP)☆14Updated 2 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆105Updated 5 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 8 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆56Updated 2 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆28Updated 3 weeks ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- ☆48Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year