Alternatives and similar repositories for cxxrtl_eval:

Users that are interested in cxxrtl_eval are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆59Updated 6 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated this week
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆40Updated this week
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 6 months ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆43Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 3 weeks ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• lambdaconcept / lambdasoc
  ☆44Updated last month
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last week
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆106Updated 5 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆76Updated 4 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated last week
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• RobertBaruch / amaranth-tutorial
  ☆41Updated 2 years ago