amaranth-lang / playground
Playground for experimenting with and sharing short Amaranth programs on the web
☆15Updated 4 months ago
Alternatives and similar repositories for playground
Users that are interested in playground are comparing it to the libraries listed below
Sorting:
- Industry standard I/O for Amaranth HDL☆28Updated 7 months ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 2 weeks ago
- An FPGA reverse engineering and documentation project☆43Updated this week
- Another size-optimized RISC-V CPU for your consideration.☆58Updated this week
- Open source Logic Analyzer based on LiteX SoC☆25Updated last month
- Wishbone bridge over SPI☆11Updated 5 years ago
- Hot Reconfiguration Technology demo☆40Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 5 months ago
- Project Trellis database☆13Updated last year
- WebAssembly-based Yosys distribution for Amaranth HDL☆26Updated 3 weeks ago
- The open-source Zynq 7000 BSP generator for openXC7☆31Updated 3 months ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆29Updated 8 months ago
- LiteX LUNA USB stack integration☆14Updated 2 years ago
- XTRX LiteX/LitePCIe based design for Julia Computing☆26Updated last year
- 妖刀夢渡☆59Updated 6 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 10 months ago
- ☆63Updated 4 years ago
- PicoRV☆44Updated 5 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- ☆41Updated 2 years ago
- Cross compile FPGA tools☆22Updated 4 years ago
- ☆13Updated 2 years ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 4 years ago
- Löwe FPGA Board☆12Updated last year
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆39Updated 2 weeks ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated last year
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago