amaranth-lang / playgroundLinks
Playground for experimenting with and sharing short Amaranth programs on the web
☆15Updated last month
Alternatives and similar repositories for playground
Users that are interested in playground are comparing it to the libraries listed below
Sorting:
- Industry standard I/O for Amaranth HDL☆29Updated 9 months ago
- An FPGA reverse engineering and documentation project☆49Updated last week
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- RFCs for changes to the Amaranth language and standard components☆18Updated this week
- Hot Reconfiguration Technology demo☆40Updated 2 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated 8 months ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆27Updated last week
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆12Updated last year
- 妖刀夢渡☆59Updated 6 years ago
- Exploring gate level simulation☆58Updated 3 months ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- Betrusted embedded controller (UP5K)☆46Updated last year
- Smol 2-stage RISC-V processor in nMigen☆26Updated 4 years ago
- Open source Logic Analyzer based on LiteX SoC☆26Updated 3 months ago
- Experiments with Yosys cxxrtl backend☆49Updated 6 months ago
- Documenting the Microchip (Atmel) ATF15xx CPLD fuse maps and programming algorithms☆59Updated last month
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Project Trellis database☆13Updated last year
- Small 32-bit RISC-V CPU with a half-width datapath inspired by the 68000☆16Updated last year
- Kicad Library to pretify your schematic with pride flags.☆15Updated 2 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆31Updated 11 months ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆44Updated 2 months ago
- A small but extremely fast safe USB DFU bootloader for both microcontroller and FPGA☆12Updated 6 months ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆29Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆19Updated last year
- Unofficial Yosys WebAssembly packages☆71Updated this week