Alternatives and similar repositories for playground

Users that are interested in playground are comparing it to the libraries listed below

• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆29Updated 11 months ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆58Updated 2 weeks ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 2 weeks ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 3 years ago
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 2 months ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆39Updated 10 months ago
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆28Updated last month
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 3 years ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆48Updated last year
• lethalbit / discretize
  A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
  ☆13Updated last year
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆72Updated this week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 11 months ago
• gregdavill / ecpprog
  Programmer for the Lattice ECP5 series, making use of FTDI based adaptors
  ☆92Updated 10 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 8 months ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆60Updated 6 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 5 months ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 4 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated 2 weeks ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆45Updated 4 months ago
• RobertBaruch / amaranth-tutorial
  ☆43Updated 2 years ago
• adamgreig / daqnet
  ☆64Updated 5 years ago
• gatecat / subprime
  ☆16Updated 4 years ago
• fallen / SucreLA
  Open source Logic Analyzer based on LiteX SoC
  ☆26Updated 5 months ago
• Wren6991 / Hazard2
  Smol 2-stage RISC-V processor in nMigen
  ☆26Updated 4 years ago
• butterstick-fpga / butterstick-bootloader
  LiteX project for the ButterStick bootloader
  ☆14Updated 2 years ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆89Updated 2 weeks ago
• kbeckmann / pergola_projects
  My pergola FPGA projects
  ☆30Updated 4 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago