trondd / oc-i2c
I2C controller core from Opencores.org
☆24Updated 13 years ago
Related projects ⓘ
Alternatives and complementary repositories for oc-i2c
- I2C controller core☆33Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- UART -> AXI Bridge☆57Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- Verilog SPI master and slave☆46Updated 8 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- UART 16550 core☆30Updated 10 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆58Updated 2 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆29Updated 3 years ago
- ☆23Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Ethernet 10GE MAC☆44Updated 10 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆29Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 6 months ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆114Updated 4 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆138Updated last year
- UART models for cocotb☆23Updated last year