I2C controller core from Opencores.org
☆27Oct 5, 2011Updated 14 years ago
Alternatives and similar repositories for oc-i2c
Users that are interested in oc-i2c are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- QSPI for SoC☆24Nov 8, 2019Updated 6 years ago
- Wishbone controlled I2C controllers☆61Aug 10, 2026Updated 3 weeks ago
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- I2C controller core☆16Jun 1, 2022Updated 4 years ago
- UART 16550 core☆42Jul 17, 2014Updated 12 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- FPGA纯逻辑实现modbus通信☆27Sep 5, 2022Updated 3 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- SPI core☆14Oct 25, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆26Oct 8, 2019Updated 6 years ago
- ☆19Oct 5, 2020Updated 5 years ago
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- 108下 計算機組織 Computer Organization 李毅郎☆12Feb 22, 2021Updated 5 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago
- GCC toolchain for MSP430☆10Apr 2, 2019Updated 7 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 12 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- FPGA implementation of an Apple//e (enhanced)☆16Mar 14, 2025Updated last year
- AHB to APB Bridge VIP☆30Mar 4, 2019Updated 7 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 12 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- Verilog VGA font generator 8 by 16 pixels☆16Mar 30, 2022Updated 4 years ago
- Verilog I2C interface for FPGA implementation☆723Feb 27, 2025Updated last year
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- ☆16May 30, 2021Updated 5 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 8 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆45Jan 18, 2024Updated 2 years ago
- Recursive unified ORAM☆15Sep 23, 2015Updated 10 years ago
- The Ultra-Low Power RISC Core☆15May 5, 2020Updated 6 years ago