Alternatives and similar repositories for oc-i2c

Users that are interested in oc-i2c are comparing it to the libraries listed below

• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆68Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆93Updated 3 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• pulp-platform / axi_spi_slave
  ☆28Updated 4 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆62Updated 9 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆99Updated 6 years ago
• antmicro / nvme-verilog-pcie
  ☆80Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆77Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆72Updated 8 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆72Updated 7 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆159Updated 10 months ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆43Updated 2 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆105Updated 7 years ago
• corundum / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆21Updated 2 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43Updated 5 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆73Updated 5 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated last year