trondd / oc-i2c
I2C controller core from Opencores.org
☆25Updated 13 years ago
Alternatives and similar repositories for oc-i2c:
Users that are interested in oc-i2c are comparing it to the libraries listed below
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- An i2c master controller implemented in Verilog☆32Updated 7 years ago
- ☆24Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Verilog SPI master and slave☆50Updated 9 years ago
- I2C controller core☆39Updated 2 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- spi memory controller☆22Updated 8 years ago
- MIPI CSI-2 RX☆31Updated 3 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated last month
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆31Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Implementation of the PCIe physical layer☆33Updated last month
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 9 months ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆122Updated 4 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago