trondd / oc-i2c
I2C controller core from Opencores.org
☆24Updated 13 years ago
Alternatives and similar repositories for oc-i2c:
Users that are interested in oc-i2c are comparing it to the libraries listed below
- UART -> AXI Bridge☆60Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated this week
- Ethernet 10GE MAC☆45Updated 10 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆41Updated 4 years ago
- Implementation of the PCIe physical layer☆32Updated 2 weeks ago
- I2C controller core☆37Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- ☆20Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- ☆23Updated 3 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Updated 7 years ago
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆28Updated 3 years ago
- ☆35Updated 9 years ago
- Interface Protocol in Verilog☆48Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Verilog SPI master and slave☆48Updated 9 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 8 months ago
- AXI4 and AXI4-Lite interface definitions☆88Updated 4 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- ☆53Updated 2 years ago
- An i2c master controller implemented in Verilog☆32Updated 7 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- UART models for cocotb☆26Updated last year