Alternatives and similar repositories for cvBench:

Users that are interested in cvBench are comparing it to the libraries listed below

• jingpu / Halide-HLS
  HLS branch of Halide
  ☆76Updated 6 years ago
• microideax / T-DLA
  ☆19Updated 5 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• cornell-zhang / facedetect-fpga
  ☆45Updated 5 years ago
• lankas / SqueezeNet
  ☆39Updated 7 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated 2 months ago
• Xilinx / pyxir
  ☆36Updated 2 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 4 years ago
• Xilinx / GO-PYNQ
  Xilinx Contest Kshitij 2019
  ☆19Updated last year
• THU-DSP-LAB / ventus-gpgpu-doc
  documentation for ventus gpgpu
  ☆16Updated 3 weeks ago
• max2ma / shiftNet
  ☆14Updated 5 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• nachiket / papaa-opencl
  OpenCL Labs for PAPAA Summer School 2016 Edition
  ☆46Updated 7 years ago
• awai54st / LUTNet
  ☆57Updated 4 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• da-steve101 / binary_connect_cifar
  An implementation of a BinaryConnect network for cifar10
  ☆11Updated 5 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated 2 years ago
• slongfield / StereoCensus
  Verilog Implementation of the Census Transform Stereo Vision algorithm
  ☆28Updated last year
• nbrummel / SIFT-implementation-in-Verilog
  Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations
  ☆38Updated 11 years ago
• atrifex / CNN-Acceleration
  Implementing CNN code in CUDA and OpenCL to evaluate its performance on NVIDIA GPUs, AMD GPUs, and an FPGA platform.
  ☆54Updated 7 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆61Updated 4 months ago
• pulp-platform / nemo
  NEural Minimizer for pytOrch
  ☆42Updated 8 months ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆29Updated 2 years ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year