Chair-for-Security-Engineering / AES_masked_BRAMLinks
Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
☆16Updated 4 years ago
Alternatives and similar repositories for AES_masked_BRAM
Users that are interested in AES_masked_BRAM are comparing it to the libraries listed below
Sorting:
- Program to scan for malicious FPGA designs.☆15Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆46Updated 2 years ago
- Open Source AES☆31Updated last year
- Side-channel analysis setup for OpenTitan☆35Updated last month
- USB virtual model in C++ for Verilog☆31Updated 10 months ago
- ☆53Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- ☆33Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- ☆34Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- HW Design Collateral for Caliptra RoT IP☆110Updated this week
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Updated 9 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- RTLMeter benchmark suite☆23Updated this week
- How to use the Intel JTAG primitive without using virtual JTAG☆17Updated 3 years ago
- ☆24Updated 4 months ago
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- SpiceBind – spice inside HDL simulator☆53Updated 2 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 7 months ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year