Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
☆16Dec 24, 2020Updated 5 years ago
Alternatives and similar repositories for AES_masked_BRAM
Users that are interested in AES_masked_BRAM are comparing it to the libraries listed below
Sorting:
- DOM Protected Hardware Implementation of AES☆26May 20, 2016Updated 9 years ago
- Read out firmware of some STM32 parts☆13Jul 20, 2025Updated 7 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- Program to scan for malicious FPGA designs.☆17Mar 20, 2021Updated 4 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- LiteX-based PCIe MITM, sniffing, fuzzing, device emulation☆19Feb 9, 2022Updated 4 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Hardware designs for fault detection☆19Apr 13, 2020Updated 5 years ago
- A hardware model checker for hyperproperties☆18Jun 14, 2024Updated last year
- ☆49Feb 26, 2023Updated 3 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆20Mar 10, 2024Updated last year
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆51Feb 19, 2026Updated 2 weeks ago
- ☆22Jul 29, 2025Updated 7 months ago
- A Python-based HDL and framework for silicon-based witchcraft☆31Feb 21, 2026Updated last week
- Files and documentation for Pico-Dirty-Blaster Workshop☆20Jun 21, 2025Updated 8 months ago
- This repository is a subset of UVVM with Utility library and BFMs, and is intended as a UVVM starting platform for thos who only need the…☆23Nov 28, 2025Updated 3 months ago
- Phase Noise Analyzer (pna_qt) - A C++/Qt desktop application for visualizing and analyzing phase noise data from CSV files. Features inte…☆24May 24, 2025Updated 9 months ago
- ☆23Feb 13, 2020Updated 6 years ago
- Java client library for integration with Freja eID☆12Feb 27, 2026Updated last week
- ☆12May 21, 2024Updated last year
- Raiden project☆24Nov 7, 2021Updated 4 years ago
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated last year
- VHDL related news.☆27Updated this week
- ☆22Oct 27, 2022Updated 3 years ago
- ☆39Dec 3, 2025Updated 3 months ago
- Side-channel analysis setup for OpenTitan☆37Nov 3, 2025Updated 4 months ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- nü-map: a somewhat-more-modern (expeirmental) derivative of umap2 for modern FaceDancer☆29Jan 4, 2024Updated 2 years ago
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Oct 20, 2019Updated 6 years ago
- VHDL PCIe Transceiver☆32Jul 2, 2020Updated 5 years ago
- Generic exploit for all version 7 (maybe others) LM32-based AMD SMU's used in APUs (and probably works on GPUs too)☆39Aug 15, 2023Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆39Mar 24, 2023Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆36Nov 13, 2025Updated 3 months ago
- ☆33Apr 30, 2023Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- ☆11Apr 3, 2017Updated 8 years ago
- Kernel module that makes it possible to create virtual wifi devices each with a virtualized stack.☆11Dec 13, 2011Updated 14 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago