Chair-for-Security-Engineering / AES_masked_BRAM
Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
☆15Updated 4 years ago
Alternatives and similar repositories for AES_masked_BRAM:
Users that are interested in AES_masked_BRAM are comparing it to the libraries listed below
- Program to scan for malicious FPGA designs.☆14Updated 4 years ago
- Side-channel analysis setup for OpenTitan☆31Updated last month
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆39Updated 2 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- ☆33Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆18Updated 4 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆21Updated last week
- Verilog Hardware Design of Ascon☆22Updated last week
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆11Updated 3 weeks ago
- Open Source AES☆31Updated last year
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- HW Design Collateral for Caliptra RoT IP☆88Updated last week
- SHA3 (KECCAK)☆18Updated 10 years ago
- ☆33Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 9 months ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- USB virtual model in C++ for Verilog☆29Updated 6 months ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 10 months ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated 6 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 5 months ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆15Updated this week
- ☆21Updated last week
- a small simple slow serial FPGA core☆16Updated 4 years ago
- Repository to store all design and testbench files for Senior Design☆18Updated 5 years ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago