Chair-for-Security-Engineering / AES_masked_BRAMLinks
Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
☆16Updated 5 years ago
Alternatives and similar repositories for AES_masked_BRAM
Users that are interested in AES_masked_BRAM are comparing it to the libraries listed below
Sorting:
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆54Updated 3 weeks ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆54Updated this week
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- Side-channel analysis setup for OpenTitan☆37Updated 2 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆48Updated 2 years ago
- ☆34Updated 4 years ago
- Open Source AES☆31Updated 3 months ago
- ☆12Updated 9 months ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Extracts specified data from a VCD file into CSV form☆10Updated 6 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Updated last year
- Program to scan for malicious FPGA designs.☆17Updated 4 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆26Updated 6 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- ☆26Updated this week
- ☆33Updated 3 years ago
- Generate symbols from HDL components/modules☆22Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year