Alternatives and similar repositories for AES_masked_BRAM

Users that are interested in AES_masked_BRAM are comparing it to the libraries listed below

• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆33Updated last week
• FPGA-Research / FPGAVirusScanner
  Program to scan for malicious FPGA designs.
  ☆14Updated 4 years ago
• rprimas / ascon-verilog
  Verilog Hardware Design of Ascon
  ☆22Updated last week
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆42Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆20Updated 4 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 10 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 8 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆13Updated 2 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• opentrng / ptrng
  Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.
  ☆11Updated 2 weeks ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆23Updated 2 weeks ago
• freecores / sha3
  SHA3 (KECCAK)
  ☆19Updated 10 years ago
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆22Updated 2 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 3 weeks ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆30Updated 7 months ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated 6 months ago