Alternatives and similar repositories for yafpgatetris

Users that are interested in yafpgatetris are comparing it to the libraries listed below

• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆74Updated 6 months ago
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆42Updated 6 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆108Updated 5 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆45Updated 2 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆36Updated last week
• OpenDGPS / zynq-axi-dma-sg
  Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
  ☆54Updated 8 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• Dmitriy0111 / nanoFOX
  A small RISC-V core (SystemVerilog)
  ☆32Updated 5 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆177Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆80Updated 5 years ago
• Des333 / soc-fpga2sdram-test
  Testing FPGA2SDRAM interface on Altera Cyclone V SoC
  ☆14Updated 10 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆82Updated 5 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆63Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• iDoka / book-mastering-fpgasic
  Mastering FPGASIC Book
  ☆18Updated 3 years ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆163Updated 6 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆42Updated 7 years ago
• WillGreen / timetoexplore
  Source code to accompany https://timetoexplore.net
  ☆63Updated 4 years ago
• blackmesalabs / s7_mini_fpga
  Example designs for the Spartan7 "S7 Mini" FPGA board
  ☆28Updated 6 years ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆117Updated last week
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• laurivosandi / hdl
  Collection of hardware description languages writings and code snippets
  ☆27Updated 10 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆93Updated 9 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆105Updated last year